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| 型号： | ADN8830ACPZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/22页 |
| 文件大小： | 0K |
| 描述： | IC THERMO COOLER CNTRLR 32-LFCSP |
| 标准包装： | 1 |
| 应用： | 热电冷却器 |
| 电流 - 电源： | 8mA |
| 电源电压： | 3.3 V ~ 5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 剪切带 (CT) |
| 其它名称： | ADN8830ACPZ-REELCT |
ADN8830
Although the FETs that drive OUT A alternate between Q1 and
Q2 being on, they have an equivalent series resistance that is
total current used by the ADN8830. The power dissipated from
the device itself is
R EQIV = D × r DS , P 1 + ( ) × r DS , N 1
equal to a weighted average of their r DS, ON values.
1 – D
The resistive power loss from the PWM transistors is then
(35)
P ADN 8830 = V DD × 10 mA (40)
There are certainly other minor mechanisms for power dissipa-
tion in the circuit. However, a rough estimate of the total power
P FET , PWM = R EQIV × I TEC
2
(36)
dissipated can be found by summing the preceding power dissi-
pation equations. Efficiency is then found by comparing the
There is also a power loss from the continuing charging and
power dissipated with the required output power to the load.
discharging of the gate capacitances on Q1 and Q2. The power
dissipated due to gate charge loss ( P GCL ) is
Efficiency =
P LOAD
P LOAD + P DISS , TOT
(41)
C ISS V DD f CLK
P GCL =
1
2
2
(37)
where
P LOAD = I LOAD × V LOAD
using the appropriate input capacitance ( C ISS ) for the NMOS
and PMOS. Both transistors are switching, so P GCL should be
calculated for each one and will be added to find the total power
dissipated from the circuit.
The series resistance of the inductor, R 2 from Figure 14, will
also exhibit a power dissipation equal to
The measured efficiency of the system will likely be less than the
calculated efficiency. Measuring the efficiency of the application
circuit is fairly simple but must be done in an exact manner to
ensure the correct numbers are being measured. Using two high
current, low impedance ammeters and two voltmeters, the cir-
cuit should be set up as shown in Figure 15.
P R 2 = R 2 × I TEC
2
(38)
POWER SUPPLY
Core loss from the inductor arises as a result of nonidealities of
the inductor. Although this is difficult to calculate explicitly, it
can be estimated as 80% of P RLS at 1 MHz switching frequen-
cies and 50% of P RL at 100 kHz. Judging conservatively
V DD
A
GND
P LOSS = 0 . 8 × P RL
(39)
V
Finally, the power dissipated by the ADN8830 is equal to the
current used by the device multiplied by the supply voltage.
ADN8830
V
A
TEC
LOAD
Again, this exact equation is difficult to determine as we have
already taken into account some of the current while finding the
gate charge loss. A reasonable estimate is to use 40 mA as the
Figure 15. Measuring Efficiency of the ADN8830 Circuit
Table V. Recommended FETs for Linear Output Amplifier
Part Number
FDW2520C *
IRF7401
IRF7233
FDR6674A
FDR840P
Type
NMOS
PMOS
NMOS
PMOS
NMOS
PMOS
C GD (nF)
0.17
0.15
0.5
2.2
0.23
0.6
Ext. C GD (nF)
2.2
1.0
1.0
C SNUB (nF)
3.3
3.3
3.3
r DS, ON (m )
18
35
22
20
9.5
12
I MAX (A)
6.0
4.5
8.7
9.5
11.5
10
Manufacturer
Fairchild
Fairchild
International Rectifier
International Rectifier
Fairchild
Fairchild
* Recommend transistors in typical application circuit Figure 1.
Table VI. Recommended FETs for PWM Output Amplifier
Part Number
FDW2520C *
Si7904DN
Si7401DN
IRF7401
IRF7404
Type
NMOS
PMOS
NMOS
PMOS
NMOS
PMOS
C ISS (nF)
1.33
1.33
1.0
3.5
1.6
1.5
r DS,ON (m )
18
35
30
17
22
40
Continuous I MAX (A)
6.0
4.5
5.3
7.3
8.7
6.7
Manufacturer
Fairchild
Fairchild
Vishay Siliconix
Vishay Siliconix
International Rectifier
International Rectifier
* Recommend transistors in typical application circuit Figure 1.
REV. D
–17 –
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