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| 型号： | ADP1043AACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 21/72页 |
| 文件大小： | 0K |
| 描述： | IC THERMO COOLER CTLR 32LFCSP |
| 标准包装： | 1,500 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.55 V |
| 电源电压： | 3.1 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1043A
LOGIC 1
LOGIC 0
Round 1
In Round 1, every supply first places its MSB on the bus. If a
supply senses that its MSB is the same as the value on the bus, it
continues to Round 2. If a supply senses that its MSB is less than
the value on the bus, it means that this supply must be a slave.
When a supply becomes a slave, it stops communicating on the
share bus because it knows that it is not the master. The supply
IDLE
PREVIOUS
BIT
t 1
t 0
t BIT
Figure 25. Share Bus High, Low, and Idle Bits
NEXT
BIT
then increases its output voltage in an attempt to share more
current.
If two units have the same MSB, they both continue to Round 2,
because either of them could be the master.
The length of a bit (t BIT ) is fixed at 10 μs. A Logic 1 is defined as
a high-to-low transition at the start of the bit and a low-to-high
transition at 75% of t BIT . A Logic 0 is defined as a high-to-low
transition at the start of the bit and a low-to-high transition at
25% of t BIT .
The bus is idle when it is high during the whole period of t BIT .
All other activity on the bus is illegal. Glitches up to t GLITCH
(200 ns) are ignored.
The digital word that represents the current information is eight
bits long. The ADP1043A takes the eight MSBs of the CS1 or CS2
reading (whichever the user chooses as the current share signal)
and uses this reading as the digital word. When read, the share
bus value at any given time is equal to the CS1 or CS2 current
reading (see Figure 26).
Digital Share Bus Scheme
Each power supply compares the digital word that it is outputting
with the digital words of all the other supplies on the bus.
PSU A
Round 2
In Round 2, all supplies that are still communicating on the bus
place their second MSB on the share bus. If a supply senses that
its MSB is less than the value on the bus, it means that this
supply must be a slave and it stops communicating.
Round 3 to Round 8
The same algorithm is repeated for up to eight rounds to allow
supplies to compare their digital words and, in this way, to
determine whether each unit is the master or a slave.
Digital Share Bus Configuration
The digital share bus can be configured in various ways.
The bandwidth of the share bus loop is programmable in
Register 0x29[2:0]. The extent to which a slave tries to match
the current of the master can be selected by programming
Register 0x2A[3:0]. The primary side or the secondary side
can be used as the current share signal by programming
Register 0x29[3].
A load line may be required between PSUs when using a digital
share bus. A minimum impedance of 15 mΩ is recommended
between the remote voltage sense node and the load.
V DD
8-BIT
WORD
MASTER
0x8F
SHAREi
SHARE
BUS
0x8F
I OUT = 35A
CS2+
1m ?
CS2–
+
35mV
–
CURRENT
SENSE
ADC
12-BIT
2293 DEC
0x8F5
DIGITAL
FILTER
÷16
8-BIT
143 DEC
0x8F
DIGITAL
WORD
SHAREo
0x8F 8-BIT
WORD
15.26μV = 1 LSB
35mV/15.26μV = 2293
Figure 26. How the Share Bus Generates the Digital Word to Place on the Digital Share Bus
Rev. 0 | Page 21 of 72
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