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参数资料
| 型号： | ADP1043AACPZ-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 56/72页 |
| 文件大小： | 0K |
| 描述： | IC THERMO COOLER CTLR 32LFCSP |
| 标准包装： | 1,500 |
| 应用： | 电源 |
| 输入电压： | 0 V ~ 1.55 V |
| 电源电压： | 3.1 V ~ 3.6 V |
| 电流 - 电源： | 20mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 带卷 (TR) |
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ADP1043A
Table 78. Register 0x53—SR1 Falling Ed ge Timing (SR1 Pin)
Bits
[7:0]
Name
t 10
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 10 time. This value is always used with
the top four bits of Register 0x54, which contains the four LSBs of the t 10 time. Each LSB
corresponds to 5 ns resolution.
Table 79. Register 0x54—SR1 Falling Ed ge Setting (SR1 Pin)
Bits
[7:4]
Name
t 10
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 10 time. This value is always used with the eight
bits of Register 0x53, which contains the eight MSBs of the t 10 time. Each LSB corresponds to
5 ns resolution.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 10 edge.
0 = no PWM modulation of the t 10 edge.
2
t 10 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 10 right.
0 = positive sign. Increase of PWM modulation moves t 10 left.
1
SR soft start setting
R/W
1 = SR signals perform a soft start every time that they are enabled.
0 = SR signals perform a soft start only the first time that they are enabled.
0
SR soft start enable
R/W
Setting this bit enables the soft start function for the SR signals.
Table 80. Register 0x55—SR2 Rising Edg e Timing (SR2 Pin)
Bits
[7:0]
Name
t 11
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 11 time. This value is always used with
the top four bits of Register 0x56, which contains the four LSBs of the t 11 time. Each LSB
corresponds to 5 ns resolution.
Table 81. Register 0x56—SR2 Rising Edg e Setting (SR2 Pin)
Bits
[7:4]
Name
t 11
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 11 time. This value is always used with the eight
bits of Register 0x55, which contains the eight MSBs of the t 11 time. Each LSB corresponds to
5 ns resolution.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 11 edge.
0 = no PWM modulation of the t 11 edge.
2
t 11 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 11 right.
0 = positive sign. Increase of PWM modulation moves t 11 left.
[1:0]
Reserved
R/W
Reserved. These bits should be set to 00 for normal operation.
Table 82. Register 0x57—SR2 Falling Ed ge Timing (SR2 Pin)
Bits
[7:0]
Name
t 12
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 12 time. This value is always used with
the top four bits of Register 0x58, which contains the four LSBs of the t 12 time. Each LSB
corresponds to 5 ns resolution.
Table 83. Register 0x58—SR2 Falling Ed ge Setting (SR2 Pin)
Bits
[7:4]
Name
t 12
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 12 time. This value is always used with the eight
bits of Register 0x57, which contains the eight MSBs of the t 12 time. Each LSB corresponds to
5 ns resolution.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 12 edge.
0 = no PWM modulation of the t 12 edge.
2
t 12 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 12 right.
0 = positive sign. Increase of PWM modulation moves t 12 left.
[1:0]
Reserved
R/W
Reserved. These bits should be set to 00 for normal operation.
Rev. 0 | Page 56 of 72
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