参数资料
| 型号： | ADP1048-600-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 28/84页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ADP1048-600 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，功率因数校正 |
| 已用 IC / 零件： | ADP1048 |
| 主要属性： | 600W，385V 输出，85~265VAC 输入 |
| 已供物品： | 板 |
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ADP1047/ADP1048
MANUFACTURER-SPECIFIC FLAG RESPONSE
Data Sheet
Four different actions can be programmed for this flag.
Manufacturer-specific flags follow a different response from the
standard PMBus flags because these flags are much faster and,
in some cases, operate on a pulse-by-pulse basis.
FAST OCP Flag Response (Register 0xFE00)
The fast OCP flag responds to an overcurrent condition that
occurs on the comparator connected to the ILIM pin. This
comparator performs a pulse-by-pulse current limiting func-
tion (see the Fast Overcurrent Protection (ILIM Pin) section).
Four different actions can be programmed for this flag using
?
?
?
?
00 (ignore, do nothing). No action is taken.
01 (shut down and soft start). The power supply is shut
down, and a soft start sequence is initiated after the delay
programmed in the VOUT_OV_FAULT_RESPONSE
register (Register 0x41, Bits[2:0]).
10 (immediate shutdown and wait for PSON). The power
supply is shut down until the PSON signal is received.
11 (disable the PWM until the flag is cleared). The PWM is
disabled until the flag is cleared; no soft start is done.
Bits[7:6]. Regardless of the programmed flag response, the PWM
pulse is always terminated when the threshold programmed for
the comparator is crossed.
OLP Flag Response (Register 0xFE02)
The OLP flag responds to differences between the OVP and
VFB pins. Open-loop protection detects a difference in voltage
?
00 (ignore, do nothing). No action is taken. The PWM
pulses are still terminated as long as the OCP condition
persists.
in excess of ~100 mV, which equates to approximately 6.6% of
the full-scale range (see the Open-Loop Protection section).
Four different actions can be programmed for this flag.
?
?
?
01 (shut down and soft start). The power supply is shut
down, and a soft start sequence is initiated after the delay
that is programmed in the IIN_OC_FAULT_RESPONSE
register (Register 0x5C, Bits[2:0]).
10 (shutdown and wait for PSON). After the number
of switching cycles programmed in Bits[5:4], the power
supply is shut down until the PSON signal is received.
11 (disable the PWM until the flag is cleared). After the
number of switching cycles programmed in Bits[5:4], the
PWM is disabled until the flag is cleared; no soft start is
?
?
?
?
00 (ignore, do nothing). No action is taken.
01 (shut down and soft start). The power supply is shut
down, and a soft start sequence is initiated after the delay
programmed in the VOUT_OV_FAULT_RESPONSE
register (Register 0x41, Bits[2:0]).
10 (immediate shutdown and wait for PSON). The power
supply is shut down until the PSON signal is received.
11 (disable the PWM until the flag is cleared). The PWM is
disabled until the flag is cleared; no soft start is done.
initiated.
FAST OVP Flag Response (Register 0xFE01)
The fast OVP flag responds to an overvoltage condition on
the programmable comparator connected to the OVP pin.
This comparator constantly monitors the output voltage and
section).
VDD and VCORE OV Flag Response (Register 0xFE03 and
Register 0xFE04)
These two flags respond to an overvoltage condition on the
VDD (3.3 V) and VCORE (2.5 V) rails. These rails must be
properly decoupled and filtered to guarantee proper operation
of the digital controller. The controller can be programmed to
ignore the flags or to shut down and restart. A debounce time
of 2.56 μs or 660 μs can be set.
The controller can also be instructed to reload the contents
of the EEPROM upon restart or to resume operation without
reloading the EEPROM contents. Reloading the contents of the
EEPROM to RAM prevents device malfunction if the RAM
contents have been corrupted during the overvoltage condition.
ILIM
FAST OCP
BLANKING AND
DEBOUNCE
TIMEOUT
1 TO 8 TIMES
TERMINATE
PWM PULSE
FLAG SET,
PROGRAMMED
ACTIONS
Figure 26. Fast OCP Flag
Rev. 0 | Page 28 of 84
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