参数资料
型号: ADP1048-600-EVALZ
厂商: Analog Devices Inc
文件页数: 79/84页
文件大小: 0K
描述: BOARD EVAL ADP1048-600
标准包装: 1
主要目的: 电源管理,功率因数校正
已用 IC / 零件: ADP1048
主要属性: 600W,385V 输出,85~265VAC 输入
已供物品:
Data Sheet
Table 148. Register 0xFE81—Latched Fla g 1
ADP1047/ADP1048
Bits
7
6
5
4
Bit Name
RSVD
EEPROM_UNLOCKED
EEPROM_CRC
I2C_ADDRESS
R/W
R
R
R
R
Description
Reserved.
1 = EEPROM is unlocked and its contents can be written.
1 = downloaded EEPROM contents are incorrect.
1 = the resistor on the ADD pin has a value that can cause an error in the address assignment
(the address falls too close to the threshold between two addresses).
3
2
1
0
LOW_LINE
FAST_OCP
SYNC_LOCK
AC_OK
R
R
R
R
1 = input voltage is higher than the high line threshold.
1 = the threshold set for the comparator on the ILIM pin has been crossed.
1 = external synchronization frequency is locked.
This flag is a programmable combination of other internal flags and refers to the condition of
the input voltage. A value of 1 means that the output of the AC_OK pin is low.
Table 149. Register 0xFE82—Latched Fla g 2
Bits
[7:6]
5
4
3
2
1
0
Bit Name
RSVD
LOW_POWER
FAST_LOOP
VCORE_OV
VDD_3.3V_OV
VDD_3.3V_UV
RSVD
R/W
R
R
R
R
R
R
R
Description
Reserved.
1 = input power has dropped below the threshold for low power mode operation.
1 = fast loop compensation filter is in use.
1 = an overvoltage condition is present on the VCORE rail.
1 = an overvoltage condition is present on the VDD rail.
1 = an undervoltage condition is present on the VDD rail.
Reserved.
PWM VALUE REGISTER
Table 150. Register 0xFE84—PWM Valu e
Bits
[7:0]
Bit Name
PWM value
R/W
R
Description
Return the eight MSBs of the PWM value (10 bits).
VAC_LINE_PERIOD REGISTER
Table 151. Register 0xFE85—VAC_LINE_PERIOD
Bits
[7:0]
Bit Name
VAC line period
R/W
R
Description
Return the measured period on the VAC pin signal. Each LSB corresponds to 163.84 μs.
READ TEMPERATURE ADC REGISTER
Table 152. Register 0xFE86—Read Temperature ADC
Bits
[15:0]
Bit Name
RTD temperature
R/W
R
Description
Return the measured temperature in ADC 12-bit format.
POWER METERING OFFSET TRIM FOR HIGH LINE INPUT REGISTER
Table 153. Register 0xFE8E—Power Metering Offset Trim for High Line Input
Bits
7
Bit Name
Offset trim polarity
R/W
R/W
Description
1 = negative offset trim is introduced.
0 = positive offset trim is introduced.
[6:0]
Power meter offset
trim
R/W
This value calibrates the power meter offset at the high line input voltage. Each LSB corresponds
to 0.0625/128 of the full input power.
Rev. 0 | Page 79 of 84
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