参数资料
型号: ADP1048-600-EVALZ
厂商: Analog Devices Inc
文件页数: 80/84页
文件大小: 0K
描述: BOARD EVAL ADP1048-600
标准包装: 1
主要目的: 电源管理,功率因数校正
已用 IC / 零件: ADP1048
主要属性: 600W,385V 输出,85~265VAC 输入
已供物品:
ADP1047/ADP1048
POWER METERING GAIN TRIM FOR HIGH LINE INPUT REGISTER
Table 154. Register 0xFE8F—Power Metering Gain Trim for High Line Input
Data Sheet
Bits
7
Bit Name
Gain trim polarity
R/W
R/W
Description
1 = negative gain trim is introduced.
0 = positive gain trim is introduced.
[6:0]
Power meter gain
trim
R/W
This value calibrates the power meter gain at the high line input voltage. Each LSB corresponds
to 0.0625/128 of the input power.
CURRENT LOOP FILTER GAIN FOR LOW LINE INPUT AND LIGHT LOAD REGISTER
Table 155. Register 0xFE90—Current Loop Filter Gain for Low Line Input and Light Load
Bits
[7:0]
Bit Name
Current loop filter
gain for low line and
R/W
R/W
Description
These bits set the current loop digital filter gain of the PFC current loop under the low line
input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.
light load
CURRENT LOOP FILTER ZERO FOR LOW LINE INPUT AND LIGHT LOAD REGISTER
Table 156. Register 0xFE91—Current Loop Filter Zero for Low Line Input and Light Load
Bits
[7:0]
Bit Name
Current loop filter
zero for low line and
R/W
R/W
Description
These bits set the current loop digital filter zero of the PFC current loop under the low line
input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.
light load
CURRENT LOOP FILTER GAIN FOR HIGH LINE INPUT AND LIGHT LOAD REGISTER
Table 157. Register 0xFE92—Current Loop Filter Gain for High Line Input and Light Load
Bits
[7:0]
Bit Name
Current loop filter
gain for high line and
R/W
R/W
Description
These bits set the current loop digital filter gain of the PFC current loop under the high line
input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.
light load
CURRENT LOOP FILTER ZERO FOR HIGH LINE INPUT AND LIGHT LOAD REGISTER
Table 158. Register 0xFE93—Current Loop Filter Zero for High Line Input and Light Load
Bits
[7:0]
Bit Name
Current loop filter
zero for high line and
R/W
R/W
Description
These bits set the current loop digital filter zero of the PFC current loop under the high line
input voltage at a light load condition if Bit 5 of Register 0xFE4F is set to 1.
light load
SMART VOUT POWER READING REGISTER
Table 159. Register 0xFE94—Smart VOUT Power Reading
Bits
[15:0]
Bit Name
Power reading
R/W
R
Description
Return the average power reading for smart output voltage (averaged over 16 full line cycles).
Rev. 0 | Page 80 of 84
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