参数资料
| 型号： | ADP1048-600-EVALZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 30/84页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL ADP1048-600 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，功率因数校正 |
| 已用 IC / 零件： | ADP1048 |
| 主要属性： | 600W，385V 输出，85~265VAC 输入 |
| 已供物品： | 板 |
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ADP1047/ADP1048
ADVANCED FEATURES
The advanced features of the ADP1047 / ADP1048 include
Data Sheet
PWM FREQUENCY SYNCHRONIZATION
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Frequency dithering for EMI noise minimization
PWM frequency synchronization with external source
Smart output voltage: real-time efficiency optimization by
changing the output voltage based on ac line and output power
Smart switching frequency: real-time efficiency
optimization by changing the switching frequency
Current loop filter for light load: real-time THD
optimization at light load conditions
Phase shedding ( ADP1048 only): real-time efficiency
optimization by shutting down one phase
Current loop feedforward: power factor and THD
optimization at light load conditions
Bridgeless boost operation ( ADP1048 only)
The part can synchronize the internal PWM clock with an
external clock frequency; the external source must be within the
minimum and maximum synchronization range programmed
in the part. To enable PWM frequency synchronization, set
Register 0xFE4F, Bit 1, to 1.
The capture range for the SYNC period is 87.5% to 112.5% of
the programmed switching period. The switching frequency
synchronized to the SYNC pin is limited by the frequency set
in Register 0xFE1B. The maximum range for the synchronized
frequency is from 89% to 114% of the programmed switching
frequency. The delay between the external SYNC signal and the
start of the internal switching cycle can be programmed using
Register 0xFE4C.
All advanced features other than bridgeless boost operation are
The part synchronizes to the external clock frequency as follows:
enabled by setting the appropriate bit in Register 0xFE4F.
FREQUENCY DITHERING (SPREAD SPECTRUM)
The PWM signal can be altered digitally to optimize for EMI
reduction (see Figure 28). For a wider but lower EMI spectrum,
the switching frequency varies with the rectified line voltage.
The switching cycle changes linearly with time from 87.5% to
112.5% of the nominal value, resulting in a frequency variation
of 114% to 89% of the nominal value.
1.
2.
3.
The part attempts to determine the external clock period,
averaging it over seven cycles (frequency capture mode).
After the period of the SYNC signal is determined, the
internal PWM clock is adjusted until the phase is also
aligned. At that point, internal and external clocks are
synchronized (phase capture mode).
Each internal switching cycle is terminated after the SYNC
rising edge is detected (pulse-by-pulse synchronization).
To enable frequency dithering, set Register 0xFE4F, Bit 0, to 1.
To configure the dithering period, program Register 0xFE1D.
V REC
TIME
SWITCHING
CYCLE
112.5% t SW
t SW
87.5% t SW
If the external SYNC signal is lost at any time or if the period
exceeds the minimum/maximum limit, the internal clock goes
back to the maximum period set in Register 0xFE1B.
During the soft start phase, the SYNC pin is ignored and the
clock frequency is not synchronized.
Interleaved operation of a multiphase PFC circuit is realized by
using the SYNC pin of several ADP1047 / ADP1048 controllers.
The frequency synchronization feature is optional. When
enabled, the switching frequency can be programmed to 1,
1/2, 1/3, or 1/4 of the SYNC frequency using Register 0xFE1E.
SMART OUTPUT VOLTAGE (LOAD LINE)
To achieve higher efficiency, the output voltage can be
programmed according to the load power and input voltage
condition (see Figure 29). To enable the smart output voltage
feature, set Register 0xFE4F, Bit 2, to 1.
OUTPUT
SWITCHING
TIME
VOH
VOH2
VOLTAGE
SUPER HIGH LINE
114% f SW
f SW
89% f SW
FREQUENCY
VOH1
VOL2
VOL1
HIGH LINE
LOW LINE
POWER
TIME
P1
P2
100%
1/f DITHER
2/f DITHER
Figure 29. Smart Output Voltage Control (Load Line)
Figure 28. Switching Frequency Dithering Control
Rev. 0 | Page 30 of 84
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