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| 型号： | ADP1740ACPZ-1.1-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 1.1V 2A 16LFCSP |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 1.1V |
| 输入电压： | 1.6 V ~ 3.6 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 2A（最小值） |
| 电流 - 限制（最小）： | 2.4A |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ EP（4x4） |
| 包装： | 标准包装 |
| 产品目录页面： | 794 (CN2011-ZH PDF) |
| 其它名称： | ADP1740ACPZ-1.1-R7DKR |
Data Sheet
THEORY OF OPERATION
The ADP1740/ADP1741 are low dropout linear regulators
that use an advanced, proprietary architecture to provide high
power supply rejection ratio (PSRR) and excellent line and load
transient response with only a small 4.7 μF ceramic output capac-
itor. Both devices operate from a 1.6 V to 3.6 V input rail and
provide up to 2 A of output current. Supply current in shutdown
mode is typically 2 μA.
ADP1740/ADP1741
The ADP1740 is available in seven fixed output voltage options
from 0.75 V to 2.5 V. The ADP1740 allows for connection of an
external soft start capacitor, which controls the output voltage
ramp during startup. The ADP1741 is an adjustable version with
an output voltage that can be set to a value from 0.75 V to 3.3 V
by an external voltage divider. Both devices are controlled by an
enable pin (EN).
SOFT START FUNCTION
VIN
ADP1740
UVLO
REVERSE POLARITY
PROTECTION
VOUT
For applications that require a controlled startup, the ADP1740/
ADP1741 provide a programmable soft start function. The
programmable soft start is useful for reducing inrush current
upon startup and for providing voltage sequencing. To implement
GND
PG
SHORT-CIRCUIT
AND THERMAL
PROTECTION
0.5V
REF
R1
R2
SENSE
soft start, connect a small ceramic capacitor from SS to GND.
Upon startup, a 0.9 μA current source charges this capacitor.
The ADP1740/ADP1741 start-up output voltage is limited by
the voltage at SS, providing a smooth ramp-up to the nominal
output voltage. The soft start time is calculated as follows:
EN
PG
DETECT
SHUTDOWN
0.9μA
SS
t SS = V REF × ( C SS / I SS )
where:
t SS is the soft start period.
V REF is the 0.5 V reference voltage.
(1)
Figure 24. ADP1740 Internal Block Diagram
C SS is the soft start capacitance from SS to GND.
I SS is the current sourced from SS (0.9 μA).
VIN
ADP1741
UVLO
REVERSE POLARITY
PROTECTION
VOUT
When the ADP1740/ADP1741 are disabled (using the EN pin),
the soft start capacitor is discharged to GND through an
internal 100 ? resistor.
2.50
2.25
GND
SHORT-CIRCUIT
2.00
EN
AND THERMAL
PROTECTION
1.75
1.50
1nF
PG
EN
PG
DETECT
SHUTDOWN
0.5V
REF
0.9μA
ADJ
SS
1.25
1.00
0.75
0.50
4.7nF
10nF
0.25
Figure 25. ADP1741 Internal Block Diagram
Internally, the ADP1740/ADP1741 consist of a reference,
an error amplifier, a feedback voltage divider, and a PMOS
pass transistor. Output current is delivered via the PMOS pass
transistor, which is controlled by the error amplifier. The error
amplifier compares the reference voltage with the feedback
voltage from the output and amplifies the difference. If the feed-
back voltage is lower than the reference voltage, the gate of the
PMOS device is pulled lower, allowing more current to pass
and increasing the output voltage. If the feedback voltage is
higher than the reference voltage, the gate of the PMOS device
is pulled higher, allowing less current to pass and decreasing the
output voltage.
Rev. F | Page 11 of 20
0
0 2 4 6 8 10
TIME (ms)
Figure 26. V OUT Ramp-Up with External Soft Start Capacitor
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