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参数资料
| 型号： | ADP1740ACPZ-1.1-R7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/20页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 1.1V 2A 16LFCSP |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 1.1V |
| 输入电压： | 1.6 V ~ 3.6 V |
| 稳压器数量： | 1 |
| 电流 - 输出： | 2A（最小值） |
| 电流 - 限制（最小）： | 2.4A |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘，CSP |
| 供应商设备封装： | 16-LFCSP-VQ EP（4x4） |
| 包装： | 标准包装 |
| 产品目录页面： | 794 (CN2011-ZH PDF) |
| 其它名称： | ADP1740ACPZ-1.1-R7DKR |
ADP1740/ADP1741
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
PIN 1
Data Sheet
VIN 1
VIN 2
VIN 3
EN 4
INDICATOR
ADP1740
TOP VIEW
(Not to Scale)
12 VOUT
11 VOUT
10 VOUT
9 SENSE
VIN 1
VIN 2
VIN 3
EN 4
INDICATOR
ADP1741
TOP VIEW
(Not to Scale)
12 VOUT
11 VOUT
10 VOUT
9 ADJ
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
Figure 3. ADP1740 Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO GND
INSIDE THE PACKAGE. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE CONNECTED TO THE GROUND PLANE ON THE BOARD.
Figure 4. ADP1741 Pin Configuration
ADP1740
1, 2, 3, 15, 16
ADP1741
1, 2, 3, 15, 16
Mnemonic
VIN
Description
Regulator Input Supply. Bypass VIN to GND with a 4.7 μF or greater capacitor. Note that all
five VIN pins must be connected to the source supply.
4
4
EN
Enable Input. Drive EN high to turn on the regulator; drive it low to turn off the regulator. For
automatic startup, connect EN to VIN.
5
5
PG
Power-Good Output. This open-drain output requires an external pull-up resistor to VIN. If
the part is in shutdown mode, current-limit mode, or thermal shutdown, or if it falls below
90% of the nominal output voltage, the PG pin immediately transitions low.
6
7
8
9
6
7
8
GND
SS
NC
SENSE
Ground.
Soft Start Pin. A capacitor connected to this pin determines the soft start time.
Not Connected. No internal connection.
Sense Input. This pin measures the actual output voltage at the load and feeds it to the error
amplifier. Connect the SENSE pin as close to the load as possible to minimize the effect of IR
drop between the regulator output and the load.
9
ADJ
Adjust Pin. A resistor divider from VOUT to ADJ sets the output voltage.
10, 11, 12,
13, 14
EP
10, 11, 12,
13, 14
EP
VOUT
Exposed
pad
Regulated Output Voltage. Bypass VOUT to GND with a 4.7 μF or greater capacitor. Note that
all five VOUT pins must be connected to the load.
The exposed pad on the bottom of the LFCSP enhances thermal performance and is
electrically connected to GND inside the package. It is recommended that the exposed pad
be connected to the ground plane on the board.
Rev. F | Page 6 of 20
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