参数资料
型号: ADP1874-0.6-EVALZ
厂商: Analog Devices Inc
文件页数: 29/44页
文件大小: 0K
描述: BOARD EVAL FOR ADP1874
标准包装: 1
系列: *
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DataSheet
EFFICIENCY CONSIDERATION
One of the important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents up to 20 A, the following are important MOSFET
parameters that aid in the selection process:
? V GS (TH) is the MOSFET voltage applied between the gate
and the source that starts channel conduction.
? R DS (ON) is the MOSFET on resistance during channel
conduction.
? Q G is the total gate charge.
? C N1 is the input capacitance of the upper side switch.
? C N2 is the input capacitance of the lower side switch.
The following are the losses experienced through the external
ADP1874/ADP1875
MOSFET Driver Loss
Other dissipative elements are the MOSFET drivers. The con-
tributing factors are the dc current flowing through a driver
during operation and the Q GATE parameter of the external MOSFETs.
P DR ( LOSS ) = V DR × ( f SW C upperFET V DR + I BIAS +
[ VREG × ( f SW C lowerFET V REG + I BIAS ) ]
where:
C upperFET is the input gate capacitance of the upper side MOSFET.
C lowerFET is the input gate capacitance of the lower side MOSFET.
I BIAS is the dc current flowing into the upper side and lower side
drivers.
V DR is the driver bias voltage (that is, the low input voltage
( VREG ) minus the rectifier drop (see Figure 87)).
VREG is the bias voltage.
component during normal switching operation:
800
VREG = 2.7V
?
?
?
?
?
Channel conduction loss (both the MOSFETs)
MOSFET driver loss
MOSFET switching loss
Body diode conduction loss (lower side MOSFET)
Inductor loss (copper and core loss)
720
640
560
480
VREG = 3.6V
VREG = 5.5V
+25°C
P N1,N2(CL) = [ D × R N1(ON) + ( 1 ? D ) × R N2(ON) ] × I LOAD
Channel Conduction Loss
During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the upper side MOSFET is directly pro-
portional to the duty-cycle (D) for each switching period, and
the power loss through the lower side MOSFET is directly
proportional to 1 ? D for each switching period. The selection
of MOSFETs is governed by the maximum dc load current that
the converter is expected to deliver. In particular, the selection
of the lower side MOSFET is dictated by the maximum load
current because a typical high current application employs duty
cycles of less than 50%. Therefore, the lower side MOSFET is
in the on state for most of the switching period.
2
400
320
240
+125°C
160
–40°C
80
300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
Figure 87. Internal Rectifier Voltage Drop vs. Switching Frequency
Switching Loss
The SW node transitions due to the switching activities of the
upper side and lower side MOSFETs. This causes removal and
replenishing of charge to and from the gate oxide layer of the
MOSFET, as well as to and from the parasitic capacitance
associated with the gate oxide edge overlap and the drain and
source terminals. The current that enters and exits these charge
paths presents additional loss during these transition times.
This can be approximately quantified by using the following
equation, which represents the time in which charge enters and
exits these capacitive regions:
t SW-TRANS = R GATE × C TOTAL
where:
C TOTAL is the C GD + C GS of the external MOSFET.
R GATE is the gate input resistance of the external MOSFET.
The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:
P SW ( LOSS ) =
t SW - TRANS
t SW
× I LOAD × V IN × 2
or
P SW(LOSS) = f SW × R GATE × C TOTAL × I LOAD × V IN × 2
Rev. A | Page 29 of 44
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