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| 型号： | ADS62C17IRGCR |
| 厂商： | Texas Instruments |
| 文件页数： | 24/68页 |
| 文件大小： | 0K |
| 描述： | IC ADC 11BIT SRL/PAR 200M 64VQFN |
| 标准包装： | 2,000 |
| 位数： | 11 |
| 采样率（每秒）： | 200M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 1.1W |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘 |
| 供应商设备封装： | 64-VQFN 裸露焊盘（9x9） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个差分，单极 |
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PIN ASSIGNMENTS (LVDS INTERFACE) – ADS62C17
SLAS631A – APRIL 2009 – REVISED JULY 2009 ............................................................................................................................................................. www.ti.com
PIN
NO.
PIN
DESCRIPTION
OF
TYPE
NAME
NUMBER
PINS
AVDD
16, 33, 34
3
I
Analog power supply
AGND
17,18,21,24,
8
I
Analog ground
27,28,31,32
CLKP, CLKM
25, 26
2
I
Differential clock input
INP_A, INM_A
29, 30
2
I
Differential analog input, Channel A
INP_B, INM_B
19, 20
2
I
Differential analog input, Channel B
VCM
23
1
IO
Internal reference mode – Common-mode voltage output.
External reference mode – Reference input. The voltage forced on this pin sets the
internal references.
RESET
12
1
I
Serial interface RESET input.
When using the serial interface mode, the user must initialize internal registers
through hardware RESET by applying a high-going pulse on this pin or by using
software reset option. Refer to Serial Interface section.
In parallel interface mode, the user has to tie RESET pin permanently high. (SCLK
and SEN are used as parallel control pins in this mode)
The pin has an internal 100 k
pull-down resistor.
SCLK
13
1
I
This pin functions as serial interface clock input when RESET is low.
It controls selection of internal or external reference when RESET is tied high. See
Table 5 for detailed information.
The pin has an internal 100 k
pull-down resistor.
SDATA
14
1
I
Serial interface data input.
The pin has an internal 100 k
pull-down resistor.
The pin has no function in parallel interface mode and can be tired to ground.
SEN
15
1
I
This pin functions as serial interface enable input when RESET is low.
It controls selection of data format and interface type when RESET is tied high.
See Table 6 for detailed information.
The pin has an internal 100 k
pull-up resistor to AVDD
SDOUT
64
1
O
This pin functions as serial interface register readout, when the <SERIAL
READOUT> bit is enabled.
When <SERIAL READOUT> = 0, this pin forces logic LOW & is not tri-stated.
CTRL1
35
1
I
Digital control input pins. Together, they control SNRBoost control and power down
CTRL2
36
1
I
modes.
CTRL3
37
1
I
CLKOUTP
57
1
O
Differential output clock, true
CLKOUTM
56
1
O
Differential output clock, complement
DA0P, DA0M
2
O
Differential output data pair, D0 and 0 multiplexed – Channel A
DA2P, DA2M
2
O
Differential output data D1 and D2 multiplexed, true – Channel A
DA4P, DA4M
2
O
Differential output data D3 and D4 multiplexed, true – Channel A
DA6P, DA6M
2
O
Differential output data D5 and D6 multiplexed, true – Channel A
DA8P, DA8M
2
O
Differential output data D7 and D8 multiplexed, true – Channel A
DA10P, DA10M
2
O
Differential output data D9 and D10 multiplexed, true – Channel A
Refer to
DB0P, DB0M
2
O
Differential output data pair, D0 and 0 multiplexed – Channel B
DB2P, DB2M
2
O
Differential output data D1 and D2 multiplexed, true – Channel B
DB4P, DB4M
2
O
Differential output data D3 and D4 multiplexed, true – Channel B
DB6P, DB6M
2
O
Differential output data D5 and D6 multiplexed, true – Channel B
DB8P, DB8M
2
O
Differential output data D7 and D8 multiplexed, true – Channel B
DB10P, DB10M
2
O
Differential output data D9 and D10 multiplexed, true – Channel B
DRVDD
1,38,48,58
4
I
Output buffer supply
30
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS62C17
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