参数资料
型号: ADS62C17IRGCR
厂商: Texas Instruments
文件页数: 6/68页
文件大小: 0K
描述: IC ADC 11BIT SRL/PAR 200M 64VQFN
标准包装: 2,000
位数: 11
采样率(每秒): 200M
数据接口: 串行,并联
转换器数目: 2
功率耗散(最大): 1.1W
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘
供应商设备封装: 64-VQFN 裸露焊盘(9x9)
包装: 带卷 (TR)
输入数目和类型: 2 个差分,单极
(5/8)AVDD
(3/8)AVDD
GND
AVDD
(5/8)AVDD
(3/8)AVDD
AVDD
GND
ToParallelPin
SERIAL INTERFACE
Register Initialization (when using serial interface only)
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
REGISTER ADDRESS
REGISTERDATA
SDATA
SCLK
SEN
RESET
t
SCLK
t
DSU
t
DH
t
SLOADS
t
SLOADH
SLAS631A – APRIL 2009 – REVISED JULY 2009 ............................................................................................................................................................. www.ti.com
Table 7. CTRL1, CTRL2 and CTRL3 Pins (continued)
CTRL1
CTRL2
CTRL3
DESCRIPTION
HIGH
LOW
Channel A standby
HIGH
MUX mode of operation, Channel A and B data is multiplexed and output
on DA10 to DA0 pins.
Figure 6. Simple Scheme to Configure Parallel Pins
The ADC has a set of internal registers, which can be accessed by the serial interface formed by pins SEN
(Serial interface Enable), SCLK (Serial Interface Clock) and SDATA (Serial Interface Data).
Serial shift of bits into the device is enabled when SEN is low. Serial data SDATA is latched at every falling edge
of SCLK when SEN is active (low). The serial data is loaded into the register at every 16th SCLK falling edge
when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be
loaded in multiple of 16-bit words within a single active SEN pulse.
The first 8 bits form the register address and the remaining 8 bits are the register data. The interface can work
with SCLK frequency from 20 MHz down to very low speeds (few Hertz) and also with non-50% SCLK duty
cycle.
After power-up, the internal registers MUST be initialized to their default values. This can be done in one of two
ways:
1.
Either through hardware reset by applying a high-going pulse on RESET pin (of width greater than 10 ns) as shown in Figure 7
OR
2.
By applying software reset. Using the serial interface, set the <RESET> bit (D7 in register 0x00) to HIGH. This initializes internal
registers to their default values and then self-resets the <RESET> bit to low. In this case the RESET pin is kept low.
Figure 7. Serial Interface Timing
14
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS62C17
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