参数资料
型号: ADS62C17IRGCR
厂商: Texas Instruments
文件页数: 46/68页
文件大小: 0K
描述: IC ADC 11BIT SRL/PAR 200M 64VQFN
标准包装: 2,000
位数: 11
采样率(每秒): 200M
数据接口: 串行,并联
转换器数目: 2
功率耗散(最大): 1.1W
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘
供应商设备封装: 64-VQFN 裸露焊盘(9x9)
包装: 带卷 (TR)
输入数目和类型: 2 个差分,单极
CLKP
VCM
2 pF
Lpkg
~ 2 nH
Lpkg
~2 nH
CLKM
Clockbuffer
Ceq
Ceq~ 1 to 3 pF, equivalentinputcapacitanceofclockbuffer
C
~1pF
bond
R
~100 W
20 W
C
~1pF
bond
R
~100 W
5kW
CLKP
CLKM
0.1 F
m
0.1 F
m
Differentialsine-wave
orPECL orLVDSclockinput
SLAS631A – APRIL 2009 – REVISED JULY 2009 ............................................................................................................................................................. www.ti.com
Figure 53. Internal Clock Buffer
For best performance, the clock inputs have to be driven differentially, reducing susceptibility to common-mode
noise. For high input frequency sampling, it is recommended to use a clock source with very low jitter. Band-pass
filtering of the clock source can help reduce the effect of jitter. There is no change in performance with a
non-50% duty cycle clock input.
Figure 54. Differential Clock Driving Circuit
Single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM tied to 1.5V common-mode voltage.
As shown in Figure 55, CLKM can be tied to VCM pin.
50
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): ADS62C17
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