参数资料
型号: ADSP-21366BSWZ-1AA
厂商: Analog Devices Inc
文件页数: 26/60页
文件大小: 0K
描述: IC DSP 32BIT 333MHZ EPAD 144LQFP
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 浮点
接口: DAI,SPI
时钟速率: 333MHz
非易失内存: ROM(512 kB)
芯片上RAM: 384kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 144-LQFP 裸露焊盘
供应商设备封装: 144-LQFP(20x20)
包装: 托盘
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Table 21. 16-Bit Memory Read Cycle
K and B Grade
Y Grade
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
t DRS
t DRH
AD15–0 Data Setup Before RD High 3.3
AD15–0 Data Hold After RD High 0
4.5
0
ns
ns
Switching Characteristics
t ALEW
t ADAS 1
t ALERW
ALE Pulse Width 2 × t PCLK – 2.0
AD15–0 Address Setup Before ALE Deasserted t PCLK – 2.5
ALE Deasserted to Read Asserted 2 × t PCLK – 3.8
2 × t PCLK – 2.0
t PCLK – 2.5
2 × t PCLK – 3.8
ns
ns
ns
t RRH 2
Delay Between RD Rising Edge to Next Falling
H + t PCLK – 1.4
H + t PCLK – 1.4
ns
Edge
t ADAH
t RWALE
t RDDRV
1
Read Deasserted to ALE Asserted F + H + 0.5
ALE Address Drive After Read High F + H + t PCLK – 2.3
AD15–0 Address Hold After ALE Deasserted t PCLK – 2.3
F + H + 0.5
F + H + t PCLK – 2.3
t PCLK – 2.3
ns
ns
ns
t ALEHZ1
t RW
ALE Deasserted to Address/Data15–0 in High-Z t PCLK
RD Pulse Width D – 2.0
t PCLK + 3.0 t PCLK
D – 2.0
t PCLK + 3.8
ns
ns
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t PCLK
H = t PCLK (if a hold cycle is specified, else H = 0)
F = 7 × t PCLK (if FLASH_MODE is set, else F = 0)
1
2
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
This parameter is only available when in EMPP = 0 mode.
ALE
t ALEW
t ALERW
t RWALE
t RRH
RD
t RW
WR
t ALEHZ
t RDDRV
t ADAS
t ADAH
t DRS
t DRH
AD15–0
VALID ADDRESS
VALID DATA
VALID DATA
VALID
ADDRESS
NOTE: FOR 16-BIT MEMORY READS, WHEN EMPP
0, ONLY ONE RD PULSE OCCURS BETWEEN ALE CYCLES.
WHEN EMPP = 0, MULTIPLE RD PULSES OCCUR BETWEEN ALE CYCLES. FOR COMPLETE INFORMATION,
SEE THE ADSP-2136x SHARC PROCESSOR HARDWARE REFERENCE.
Figure 18. Read Cycle for 16-Bit Memory Timing
Rev. J |
Page 26 of 60 |
July 2013
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