参数资料
型号: ADSP-BF524KBCZ-4
厂商: Analog Devices Inc
文件页数: 35/88页
文件大小: 0K
描述: IC DSP CTRLR 400MHZ 289CSPBGA
标准包装: 1
系列: Blackfin®
类型: 定点
接口: DMA,I²C,PPI,SPI,SPORT,UART,USB
时钟速率: 400MHz
非易失内存: ROM(32 kB)
芯片上RAM: 132kB
电压 - 输入/输出: 1.8V,2.5V,3.3V
电压 - 核心: 1.30V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 289-LFBGA,CSPBGA
供应商设备封装: 289-CSPBGA(12x12)
包装: 托盘
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Total Power Dissipation
Total power dissipation has two components:
1. Static, including leakage current
2. Dynamic, due to transistor switching characteristics
Many operating conditions can also affect power dissipation,
including temperature, voltage, operating frequency, and pro-
cessor activity. Electrical Characteristics on Page 32 shows the
The ASF is combined with the CCLK Frequency and V DDINT
dependent data in Table 23 or Table 25 to calculate this part.
The second part is due to transistor switching in the system
clock (SCLK) domain, which is included in the I DDINT specifica-
tion equation.
Table 21. Activity Scaling Factors (ASF) 1
current dissipation for internal circuitry (V DDINT ). I DDDEEPSLEEP
specifies static power dissipation as a function of voltage
(V DDINT ) and temperature (see Table 22 or Table 24 ), and I DDINT
specifies the total power specification for the listed test condi-
tions, including the dynamic component as a function of voltage
(V DDINT ) and frequency ( Table 23 or Table 25 ).
I DDINT Power Vector
I DD-PEAK
I DD-HIGH
I DD-TYP
I DD-APP
Activity Scaling Factor (ASF)
1.29
1.26
1.00
0.88
There are two parts to the dynamic component. The first part is
due to transistor switching in the core clock (CCLK) domain.
This part is subject to an Activity Scaling Factor (ASF) which
represents application code running on the processor core and
L1 memories ( Table 21 ).
1
I DD-NOP 0.72
I DD-IDLE 0.44
See Estimating Power for ASDP-BF534/BF536/BF537 Blackfin Processors
(EE-297) . The power vector information also applies to the ADSP-BF52x
processors.
Table 22. Static Current — I DD-DEEPSLEEP (mA) for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Voltage (V DDINT ) 1
T J (°C)
–40
–20
0
25
40
55
70
85
100
105
1.2 V
1.47
1.67
1.97
2.49
3.12
4.07
5.77
8.32
12.11
13.78
1.25 V
1.42
1.81
2.07
2.66
3.37
4.47
6.28
8.88
12.93
14.72
1.3 V
1.50
1.89
2.15
2.79
3.57
4.82
6.71
9.56
13.94
15.74
1.35 V 1.4 V
1.64 1.85
1.95 2.01
2.22 2.30
2.92 3.07
3.75 3.96
5.11 5.41
7.17 7.61
10.25 10.94
14.76 15.76
16.81 17.91
1.45 V
2.12
2.07
2.39
3.20
4.18
5.73
8.09
11.63
16.77
19.06
1.5 V
2.09
2.12
2.47
3.36
4.40
6.06
8.60
12.36
17.83
20.27
1
Valid temperature and voltage ranges are model-specific. See Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on Page 28 .
Table 23. Dynamic Current in CCLK Domain (mA, with ASF = 1.0) 1 for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
f CCLK
Voltage (V DDINT ) 2
(MHz) 2
400
350
300
250
200
100
1.2 V
N/A
N/A
63.31
53.36
43.49
23.6
1.25 V
N/A
N/A
66.51
56.10
45.76
24.93
1.3 V
91.41
80.56
69.78
58.88
48.08
26.29
1.35 V 1.4 V
95.7 100.11
84.37 88.26
73.09 76.51
61.72 64.64
50.44 52.86
27.68 29.12
1.45 V
104.51
92.17
79.93
67.56
55.28
30.56
1.5 V
109.01
96.17
83.42
70.55
57.77
32.04
1
2
The values are not guaranteed as standalone maximum specifications. They must be combined with static current per the equations of Electrical Characteristics on Page 32 .
Valid frequency and voltage ranges are model-specific. See Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors on Page 28 .
Rev. D |
Page 35 of 88 | July 2013
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