参数资料
型号: ADSP-BF527KBCZ-6A
厂商: Analog Devices Inc
文件页数: 37/88页
文件大小: 0K
描述: IC DSP 16BIT 600MHZ 208CSPBGA
产品变化通告: Datasheet Specification Change 14/Dec/2009
标准包装: 1
系列: Blackfin®
类型: 定点
接口: DMA,以太网,I²C,PPI,SPI,SPORT,UART,USB
时钟速率: 600MHz
非易失内存: ROM(32 kB)
芯片上RAM: 132kB
电压 - 输入/输出: 1.8V,2.5V,3.3V
电压 - 核心: 1.10V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 208-LFBGA,CSPBGA
供应商设备封装: 208-CSPBGA
包装: 托盘
配用: EVAL-SDP-CB1Z-ND - BOARD EVALUATION FOR SDP-CB1
ADZS-BF527-MPSKIT-ND - BOARD EVAL MEDIA PLAYER BF527
ADZS-BF527-EZLITE-ND - BOARD EVAL ADSP-BF527
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in Table 26 may cause perma-
nent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other condi-
Table 26. Absolute Maximum Ratings
tions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
Parameter
Internal Supply Voltage (V DDINT ) for ADSP-BF523/ADSP-BF525/ADSP-BF527 processors
Internal Supply Voltage (V DDINT ) for ADSP-BF522/ADSP-BF524/ADSP-BF526 processors
External (I/O) Supply Voltage (V DDEXT /V DDMEM )
Real-Time Clock Supply Voltage (V DDRTC )
OTP Supply Voltage (V DDOTP )
OTP Programming Voltage (V PPOTP ) 1
OTP Programming Voltage (V PPOTP ) 2
USB PHY Supply Voltage (V DDUSB )
Input Voltage 3, 4, 5
Input Voltage 3, 4, 6
Rating
–0.3 V to +1.26 V
–0.3 V to +1.47 V
–0.3 V to +3.8 V
–0.5 V to +3.8 V
–0.5 V to +3.0 V
–0.5 V to +3.0 V
–0.5 V to +7.1 V
–0.5 V to +3.8 V
–0.5 V to +3.8 V
–0.5 V to +5.5 V
Input Voltage
3, 4, 7
–0.5 V to +5.25 V
Output Voltage Swing
–0.5 V to V DDEXT /V DDMEM + 0.5 V
I OH /I OL Current per Pin Group
3, 8
82 mA (max)
Storage Temperature Range
Junction Temperature While Biased
–65°C to +150°C
+110°C
1
2
3
4
5
6
7
8
Applies to OTP memory reads and writes for ADSP-BF523/ADSP-BF525/ADSP-BF527 processors and to OTP memory reads for ADSP-BF522/ADSP-BF524/ADSP-BF526
processors.
Applies only to OTP memory writes for ADSP-BF522/ADSP-BF524/ADSP-BF526 processors.
Applies to 100% transient duty cycle.
Applies only when V DDEXT is within specifications. When V DDEXT is outside specifications, the range is V DDEXT ±0.2 V.
For other duty cycles see Table 27 .
Applies to balls SCL and SDA.
Applies to balls USB_DP, USB_DM, and USB_VBUS.
For pin group information, see Table 28 . For other duty cycles see Table 29 .
Table 27. Maximum Duty Cycle for Input Transient Volt-
age 1, 2
Table 26 specifies the maximum total source/sink (I OH /I OL ) cur-
rent for a group of pins. Permanent damage can occur if this
Maximum Duty Cycle 3
100%
40%
25%
15%
V IN Min (V) 4
–0.50
–0.70
–0.80
–0.90
V IN Max (V) 6
+3.80
+4.00
+4.10
+4.20
value is exceeded. To understand this specification, if pins PH4,
PH3, PH2, PH1, and PH0 from group 1 in Table 28 were sourc-
ing or sinking 2 mA each, the total current for those pins would
be 10 mA. This would allow up to 72 mA total that could be
sourced or sunk by the remaining pins in the group without
damaging the device. For a list of all groups and their pins, see
the Table 28 table. For duty cycles that are less than 100%, see
Applies to all signal balls with the exception of CLKIN, XTAL, VR OUT /
10% –1.00 +4.30
1
EXT_WAKE1, SCL, SDA, USB_DP, USB_DM, and USB_VBUS.
Table 29 . Note that the V OH and V OL specifications have separate
per-pin maximum current requirements (see Table 19 on
Page 33 and Table 20 on Page 34 ).
2
3
Applies only when V DDEXT is within specifications. When V DDEXT is outside specifi-
cations, the range is V DDEXT ±0.2 V.
Duty cycle refers to the percentage of time the signal exceeds the value for the 100%
Table 28. Total Current Pin Groups
case. The is equivalent to the measured duration of a single instance of overshoot
Group
Pins in Group
4
or undershoot as a percentage of the period of occurrence.
The individual values cannot be combined for analysis of a single instance of
overshoot or undershoot. The worst case observed value must fall within one of the
voltages specified, and the total duration of the overshoot or undershoot (exceeding
the 100% case) must be less than or equal to the corresponding duty cycle.
1
2
3
4
5
PH4, PH3, PH2, PH1, PH0, PF15, PF14, PF13
PF12, SDA, SCL, PF11, PF10, PF9, PF8, PF7
PF6, PF5, PF4, PF3, PF2, PF1, PF0, PPI_FS1
PPI_CLK, PG15, PG14, PG13, PG12, PG11, PG10, PG9
PG8, PG7, PG6, PG5, PG4, BMODE3, BMODE2, BMODE1
Rev. D |
Page 37 of 88 | July 2013
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