- 您现在的位置：买卖IC网 > PDF目录19504 > ADSP-BF527KBCZ-6A (Analog Devices Inc)IC DSP 16BIT 600MHZ 208CSPBGA PDF资料下载
参数资料
| 型号： | ADSP-BF527KBCZ-6A |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/88页 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 600MHZ 208CSPBGA |
| 产品变化通告： | Datasheet Specification Change 14/Dec/2009 |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | 定点 |
| 接口： | DMA，以太网，I²C，PPI，SPI，SPORT，UART，USB |
| 时钟速率： | 600MHz |
| 非易失内存： | ROM（32 kB） |
| 芯片上RAM： | 132kB |
| 电压 - 输入/输出： | 1.8V，2.5V，3.3V |
| 电压 - 核心： | 1.10V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 208-LFBGA，CSPBGA |
| 供应商设备封装： | 208-CSPBGA |
| 包装： | 托盘 |
| 配用： | EVAL-SDP-CB1Z-ND - BOARD EVALUATION FOR SDP-CB1 ADZS-BF527-MPSKIT-ND - BOARD EVAL MEDIA PLAYER BF527 ADZS-BF527-EZLITE-ND - BOARD EVAL ADSP-BF527 |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Table 3. System Interrupt Controller (SIC) (Continued)
General Purpose
Default
Peripheral Interrupt Event
OTP Memory Interrupt
GP Counter
DMA Channel 1 (MAC RX/HOSTDP)
Port H Interrupt A
DMA Channel 2 (MAC TX/NFC)
Port H Interrupt B
Timer 0
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
Timer 7
Port G Interrupt A
Port G Interrupt B
MDMA Stream 0
MDMA Stream 1
Software Watchdog Timer
Port F Interrupt A
Port F Interrupt B
SPI Status
NFC Status
HOSTDP Status
Host Read Done
Reserved
USB_INT0 Interrupt
USB_INT1 Interrupt
USB_INT2 Interrupt
USB_DMAINT Interrupt
Interrupt (at RESET)
IVG11
IVG11
IVG11
IVG11
IVG11
IVG11
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG12
IVG13
IVG13
IVG13
IVG13
IVG13
IVG7
IVG7
IVG7
IVG7
IVG10
IVG10
IVG10
IVG10
IVG10
Peripheral Interrupt ID
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
Core Interrupt ID
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
0
0
0
0
3
3
3
3
3
SIC Registers
IAR3 IMASK0, ISR0, IWR0
IAR3 IMASK0, ISR0, IWR0
IAR3 IMASK0, ISR0, IWR0
IAR3 IMASK0, ISR0, IWR0
IAR3 IMASK0, ISR0, IWR0
IAR3 IMASK0, ISR0, IWR0
IAR4 IMASK1, ISR1, IWR1
IAR4 IMASK1, ISR1, IWR1
IAR4 IMASK1, ISR1, IWR1
IAR4 IMASK1, ISR1, IWR1
IAR4 IMASK1, ISR1, IWR1
IAR4 IMASK1, ISR1, IWR1
IAR4 IMASK1, ISR1, IWR1
IAR4 IMASK1, ISR1, IWR1
IAR5 IMASK1, ISR1, IWR1
IAR5 IMASK1, ISR1, IWR1
IAR5 IMASK1, ISR1, IWR1
IAR5 IMASK1, ISR1, IWR1
IAR5 IMASK1, ISR1, IWR1
IAR5 IMASK1, ISR1, IWR1
IAR5 IMASK1, ISR1, IWR1
IAR5 IMASK1, ISR1, IWR1
IAR6 IMASK1, ISR1, IWR1
IAR6 IMASK1, ISR1, IWR1
IAR6 IMASK1, ISR1, IWR1
IAR6 IMASK1, ISR1, IWR1
IAR6 IMASK1, ISR1, IWR1
IAR6 IMASK1, ISR1, IWR1
IAR6 IMASK1, ISR1, IWR1
IAR6 IMASK1, ISR1, IWR1
Event Control
The processor provides a very flexible mechanism to control the
processing of events. In the CEC, three registers are used to
coordinate and control events. Each register is 16 bits wide.
? CEC interrupt latch register (ILAT) — Indicates when
events have been latched. The appropriate bit is set when
the processor has latched the event and cleared when the
event has been accepted into the system. This register is
updated automatically by the controller, but it may be writ-
ten only when its corresponding IMASK bit is cleared.
? CEC interrupt mask register (IMASK) — Controls the
masking and unmasking of individual events. When a bit is
set in the IMASK register, that event is unmasked and is
processed by the CEC when asserted. A cleared bit in the
IMASK register masks the event, preventing the processor
from servicing the event even though the event may be
latched in the ILAT register. This register may be read or
written while in supervisor mode. (Note that general-
purpose interrupts can be globally enabled and disabled
with the STI and CLI instructions, respectively.)
? CEC interrupt pending register (IPEND) — The IPEND
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Each
register contains a bit corresponding to each of the peripheral
? SIC interrupt mask registers (SIC_IMASKx) — Control the
masking and unmasking of each peripheral interrupt event.
When a bit is set in these registers, that peripheral event is
Rev. D | Page 8 of 88 | July 2013
相关PDF资料 |
PDF描述 |
|---|---|
| TAJB106K020H | CAP TANT 10UF 20V 10% 1210 |
| XC9536XL-7VQ44I | IC CPLD 36MCELL 7.5NS 44VQFP |
| GA355DR7GB223KY02L | CAP CER 0.022UF 250V 10% 2220 |
| ADP3338AKC-2.85-R7 | IC REG LDO 2.85V 1A SOT-223 |
| ADSP-BF525KBCZ-6A | IC DSP 16BIT 600MHZ 208CSPBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-BF527KBCZ-6AX | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-BF527KBCZ6C1X | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-BF527KBCZ-6C2 | 功能描述:IC DSP 16BIT 600MHZ 289CSPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF527KBCZ6C2X | 制造商:Analog Devices 功能描述: |
| ADSP-BF527KBCZ-6X | 制造商:Analog Devices 功能描述:DSP 32-Bit 600MHz 208-Pin CSP-BGA 制造商:Analog Devices 功能描述:- Trays |
发布紧急采购，3分钟左右您将得到回复。