- 您现在的位置：买卖IC网 > PDF目录19389 > ADSP-BF544MBBCZ-5M (Analog Devices Inc)IC DSP 16BIT 533MHZ MDDR 400CBGA PDF资料下载
参数资料
| 型号： | ADSP-BF544MBBCZ-5M |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/100页 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 533MHZ MDDR 400CBGA |
| 标准包装： | 1 |
| 系列： | Blackfin® |
| 类型： | 定点 |
| 接口： | CAN，SPI，SSP，TWI，UART |
| 时钟速率： | 533MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 196kB |
| 电压 - 输入/输出： | 2.50V，3.30V |
| 电压 - 核心： | 1.25V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 400-LFBGA，CSPBGA |
| 供应商设备封装： | 400-CSPBGA（17x17） |
| 包装： | 托盘 |
| 配用： | ADZS-BF548-EZLITE-ND - KIT EZLITE ADZS-BF548 |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页
Rev. C
|
Page 16 of 100
|
February 2010
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
key is meant to be pressed. It is possible to detect when multiple
keys are pressed simultaneously and to provide limited key reso-
lution capability when this happens.
SECURE DIGITAL (SD)/SDIO CONTROLLER
The SD/SDIO controller is a serial interface that stores data at a
data rate of up to 10M bytes per second using a 4-bit data line.
The SD/SDIO controller supports the SD memory mode only.
The interface supports all the power modes and performs error
checking by CRC.
CODE SECURITY
An OTP/security system, consisting of a blend of hardware and
software, provides customers with a flexible and rich set of code
security features with Lockbox
secure technology. Key features
include:
OTP memory
Unique chip ID
Code authentication
Secure mode of operation
The security scheme is based upon the concept of authentica-
tion of digital signatures using standards-based algorithms and
provides a secure processing environment in which to execute
code and protect assets. See Lockbox Secure Technology Dis-
MEDIA TRANSCEIVER MAC LAYER (MXVR)
The ADSP-BF549 Blackfin processors provide a media trans-
ceiver (MXVR) MAC layer, allowing the processor to be
connected directly to a MOST
1 network through an FOT. See
Figure 5 on Page 17 for an example of a MXVR MOST
connection.
The MXVR is fully compatible with industry-standard standal-
one MOST controller devices, supporting 22.579 Mbps or
24.576 Mbps data transfer. It offers faster lock times, greater jit-
ter immunity, and a sophisticated DMA scheme for data
transfers. The high speed internal interface to the core and L1
memory allows the full bandwidth of the network to be utilized.
The MXVR can operate as either the network master or as a net-
work slave.
The MXVR supports synchronous data, asynchronous packets,
and control messages using dedicated DMA channels that oper-
ate autonomously from the processor core moving data to and
from L1 and/or L2 memory. Synchronous data is transferred to
or from the synchronous data physical channels on the MOST
bus through eight programmable DMA channels. The synchro-
nous data DMA channels can operate in various modes
including modes that trigger DMA operation when data pat-
terns are detected in the receive data stream. Furthermore, two
DMA channels support asynchronous traffic, and two others
support control message traffic.
Interrupts are generated when a user-defined amount of syn-
chronous data has been sent or received by the processor or
when asynchronous packets or control messages have been sent
or received.
The MXVR peripheral can wake up the ADSP-BF549 Blackfin
processor from sleep mode when a wakeup preamble is received
over the network or based on any other MXVR interrupt event.
Additionally, detection of network activity by the MXVR can be
used to wake up the ADSP-BF549 Blackfin processor from the
hibernate state. These features allow the ADSP-BF549 processor
to operate in a low-power state when there is no network activ-
ity or when data is not currently being received or transmitted
by the MXVR.
The MXVR clock is provided through a dedicated external crys-
tal or crystal oscillator. The frequency of the external crystal or
crystal oscillator can be 256 Fs, 384 Fs, 512 Fs, or 1024 Fs for
Fs = 38 kHz, 44.1 kHz, or 48 kHz. If using a crystal to provide
the MXVR clock, use a parallel-resonant, fundamental mode,
microprocessor-grade crystal.
DYNAMIC POWER MANAGEMENT
The ADSP-BF54x Blackfin processors provide five operating
modes, each with a different performance/power profile. In
addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
further reducing power dissipation. Control of clocking to each
of the ADSP-BF54x Blackfin processors’ peripherals also
reduces power consumption. See Table 5 for a summary of the
power settings for each mode.
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing the capability to run at the maximum operational fre-
quency. This is the power-up default execution state in which
maximum performance can be achieved. The processor core
and all enabled peripherals run at full speed.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.
In the active mode, it is possible to disable the control input to
the PLL by setting the PLL_OFF bit in the PLL control register.
This register can be accessed with a user-callable routine in the
on-chip ROM called bfrom_SysControl(). For more informa-
tion, see the “Dynamic Power Management” chapter in the
ADSP-BF54x Blackfin Processor Hardware Reference. If dis-
abled, the PLL must be re-enabled before transitioning to the
full-on or sleep modes.
1 MOST is a registered trademark of Standard Microsystems, Corp.
相关PDF资料 |
PDF描述 |
|---|---|
| SWS600L-5 | POWER SUPPLY 5V 120A SGL OUTPUT |
| ADSP-BF544BBCZ-5A | IC DSP 16BIT 533MHZ 400CSBGA |
| ADSP-21266SKSTZ-2D | IC DSP 32BIT 150MHZ 144-LQFP |
| ADSP-BF534BBC-5A | IC DSP CTLR 16BIT 182CSPBGA |
| MAX6643LBBAEE+T | IC CNTRLR FAN SPEED 16-QSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADSP-BF547BBCZ-5A | 功能描述:IC DSP 16BIT 533MHZ 400CSBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF547BBCZ-5X | 制造商:Analog Devices 功能描述:- Trays |
| ADSP-BF547BBCZC11 | 制造商:Analog Devices 功能描述: |
| ADSP-BF547KBCZ-6A | 功能描述:IC DSP 600MHZ 400CSPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| ADSP-BF547MBBCZ-5M | 功能描述:IC DSP 16BIT 533MHZ MDDR 400CBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:Blackfin® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
发布紧急采购，3分钟左右您将得到回复。