参数资料
| 型号： | ADUC7122BBCZ-RL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 27/96页 |
| 文件大小： | 0K |
| 描述： | PRECISION ANALOG MCU I.C |
| 标准包装： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心处理器： | ARM7 |
| 芯体尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 126KB（63K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 8K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 13x12b，D/A 12x12b |
| 振荡器型： | 内部 |
| 工作温度： | -10°C ~ 95°C |
| 封装/外壳： | 108-LFBGA，CSPBGA |
| 包装： | 标准包装 |
| 其它名称： | ADUC7122BBCZ-RLDKR |
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ADuC7122
Rev. 0 | Page 33 of 96
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture is described for the three different modes of
operation: differential mode, pseudo differential mode, and
single-ended mode.
Differential Mode
The ADuC7122 contains a successive approximation ADC
based on two capacitive DACs. Figure 18 and Figure 19 show
simplified schematics of the ADC in acquisition and conversion
phase, respectively. The ADC comprises control logic, a SAR, and
two capacitive DACs. In Figure 18 (the acquisition phase), SW3
is closed and SW1 and SW2 are in Position A. The comparator
is held in a balanced condition, and the sampling capacitor
arrays acquire the differential signal on the input.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
CHANNEL+
CHANNEL–
08
75
5-
0
18
ADC0
ADC10
MUX
Figure 18. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 19), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected when the
conversion begins. The control logic and the charge redistribution
DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator back
into a balanced condition. When the comparator is rebalanced,
the conversion is complete. The control logic generates the ADC
output code. The output impedances of the sources driving the
VIN+ and VIN inputs must be matched; otherwise, the two inputs
have different settling times, resulting in errors. The input
channel configuration for differential mode is set using the
ADCCP and ADCCN registers.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
CHANNEL+
CHANNEL–
087
55-
019
ADC0
ADC10
MUX
Figure 19. ADC Conversion Phase
Pseudo Differential Mode
In pseudo differential mode, Channel is linked to the VIN input
of the ADuC7122, and SW2 switches between A (Channel)
and B (VREF). The VIN input must be connected to ground or a
low voltage. The input signal on VIN+ can then vary from VIN to
VREF + VIN. Note that VIN must be selected so that VREF + VIN
does not exceed AVDD. In pseudo differential mode, only AINCM
or PADCxN should be enabled for the VIN channel. The ADCCN
register is used to set Channel to AINCM or PADCxN, and
the Channel+ can be selected using the ADCCP register.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
SW2
CS
VREF
ADC0
ADC9
VIN–
MUX
CHANNEL+
CHANNEL–
087
55-
020
PADCxP
Figure 20. ADC in Pseudo Differential Mode
Single-Ended Mode
In single-ended mode, SW2 is always connected internally to
ground. The VIN input can be floating. The input signal range
on VIN+ is 0 V to VREF. The ADuC7122 has 11 fixed gain ADC
channels and two programmable gain ADC channels, which are
enabled using the ADCCP register.
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
B
CS
ADC0
ADC10
MUX
CHANNEL+
CHANNEL–
087
55-
021
Figure 21. ADC in Single-Ended Mode
Analog Input Structure
Figure 22 shows the equivalent circuit of the analog input
structure of the ADC. The four diodes provide ESD protection
for the analog inputs. Care must be taken to ensure that the
analog input signals never exceed the supply rails by more than
300 mV. Voltage in excess of 300 mV can cause these diodes to
become forward biased and start conducting into the substrate.
These diodes can conduct up to 10 mA without causing irreversi-
ble damage to the part.
The C1 capacitors in Figure 22 are typically 4 pF and can be
primarily attributed to pin capacitance. The resistors are lumped
components made up of the on resistance of the switches. The
value of these resistors is typically about 100 Ω. The C2 capacitors
are the ADC sampling capacitors and have a capacitance of 16 pF
typical.
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