参数资料
型号: ADUC7122BBCZ-RL
厂商: Analog Devices Inc
文件页数: 60/96页
文件大小: 0K
描述: PRECISION ANALOG MCU I.C
标准包装: 1
系列: MicroConverter® ADuC7xxx
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 41.78MHz
连通性: I²C,SPI,UART/USART
外围设备: POR,PWM,WDT
输入/输出数: 32
程序存储器容量: 126KB(63K x 16)
程序存储器类型: 闪存
RAM 容量: 8K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 13x12b,D/A 12x12b
振荡器型: 内部
工作温度: -10°C ~ 95°C
封装/外壳: 108-LFBGA,CSPBGA
包装: 标准包装
其它名称: ADUC7122BBCZ-RLDKR
ADuC7122
Rev. 0 | Page 63 of 96
I2C Address 0 Register
Name:
I2C0ADR0, I2C1ADR0
Address:
0xFFFF0898, 0xFFFF0918
Default Value:
0x00, 0x00
Access:
Read/write
Function:
This 8-bit MMR holds the 7-bit slave address +
the read/write bit when the master begins
communicating with a slave.
I2C Address 1 Register
Name:
I2C0ADR1, I2C1ADR1
Address:
0xFFFF089C, 0xFFFF091C
Default Value:
0x00, 0x00
Access:
Read/write
Function:
This 8-bit MMR is used in 10-bit addressing
mode only. This register contains the least
significant byte of the address.
I2C Master Clock Control Register
Name:
I2C0DIV, I2C1DIV
Address:
0xFFFF08A4, 0xFFFF0924
Default Value:
0x1F1F, 0x1F1F
Access:
Read/write
Function:
This MMR controls the frequency of the I2C
clock generated by the master on to the SCL
pin. For further details, see the I2C section.
I2C Start Byte Register
Name:
I2C0SBYTE, I2C1SBYTE
Address:
0xFFFF08A0, 0xFFFF0920
Default Value:
0x00, 0x00
Access:
Read/write
Function:
This MMR can be used to generate a start byte
at the start of a transaction.
To generate a start byte followed by a normal address, first write
to I2CxSBYTE, then write to the address register (I2CxADRx).
This drives the byte written in I2CxSBYTE onto the bus fol-
lowed by a repeated start. This register can be used to drive any
byte onto the I2C bus followed by a repeated start (not a start
byte only, for example, 00000001).
Table 104. I2CxADR0 MMR in 7-Bit Address Mode (Address = 0xFFFF0898, 0xFFFF0918, Default Value = 0x00)
Bit
Name
Description
7:1
I2CADR
These bits contain the 7-bit address of the required slave device.
0
R/W
Bit 0 is the read/write bit.
When this bit = 1, a read sequence is requested.
When this bit = 0, a write sequence is requested.
Table 105. I2CxADR0 MMR in 10-Bit Address Mode
Bit
Name
Description
7:3
These bits must be set to [11110b] in 10-bit address mode.
2:1
I2CMADR
These bits contain ADDR[9:8] in 10-bit addressing mode.
0
R/W
Read/write bit.
When this bit = 1, a read sequence is requested.
When this bit = 0, a write sequence is requested.
Table 106. I2CxADR1 MMR in 10-Bit Address Mode
Bit
Name
Description
7:0
I2CLADR
These bits contain ADDR[7:0] in 10-bit addressing mode.
Table 107. I2CxDIV MMR
Bit
Name
Description
15:8
DIVH
These bits control the duration of the high period of SCLx.
7:0
DIVL
These bits control the duration of the low period of SCLx.
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