参数资料
| 型号： | ADV7391BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 50/108页 |
| 文件大小： | 0K |
| 描述： | IC ENCODER VIDEO W/DAC 32LFCSP |
| 产品变化通告： | ADV734x, ADV739x Feature Improvement |
| 标准包装： | 1 |
| 类型： | 视频编码器 |
| 应用： | 机顶盒，视频播放器，显示器 |
| 电压 - 电源，模拟： | 2.6 V ~ 3.46 V |
| 电压 - 电源，数字： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 托盘 |
| 配用： | EVAL-ADV7391EBZ-ND - BOARD EVAL FOR ADV7391 ENCODER |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页当前第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 46 of 108
ADV7390/ADV7391 INPUT CONFIGURATION
The ADV7390/ADV7391 support a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7390/ADV7391 default to standard definition
(SD) mode on power-up. Table 35 provides an overview of all
possible input configurations. Each input mode is described in
detail in this section. Note that the WLCSP option is only
configured to support SD as shown in Figure 51.
Table 35. ADV7390/ADV7391 Input Configuration
Input Mode
P7
P6
P5
P4
P3
P2
P1
P0
000
SD
YCrCb
010
ED/HD-DDR
YCrCb
111
ED (at 54 MHz)
YCrCb
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
SD YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 27 MHz. A 27 MHz clock signal must be
provided on the CLKIN pin. If required, external synchroni-
zation signals can be provided on the HSYNC and VSYNC pins.
Embedded EAV/SAV timing codes are also supported. The
ITU-R BT.601/656 input standard is supported. The interleaved
pixel data is input on Pin P7 to Pin P0, with Pin P0 being the LSB.
Figure 51. SD Example Application
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 010
Enhanced definition (ED) or high definition (HD) YCrCb data
can be input in an interleaved 4:2:2 format over an 8-bit DDR
bus. The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported.
8-Bit 4:2:2 ED/HD YCrCb Mode (DDR)
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input
on Pin P7 to Pin P0 on either the rising or falling edge of CLKIN.
Pin P0 is the LSB.
The CrCb pixel data is also input on Pin P7 to Pin P0 on the
opposite edge of CLKIN. Pin P0 is the LSB.
Whether the Y data is clocked in on the rising or falling edge of
CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 52
and Figure 53).
Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
Figure 54. ED/HD-DDR Example Application
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
The interleaved pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
Figure 55. ED (at 54 MHz) Input Sequence (EAV/SAV)
MPEG2
DECODER
CLKIN
P[7:0]
27MHz
YCrCb
ADV7390/
ADV7391
VSYNC,
HSYNC
2
8
06234-
049
3FF
00
XY
Y0
Y1
Cr0
CLKIN
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
P[7:0]
Cb0
06234-
050
3FF
00
XY
Cb0
Cr0
Y1
CLKIN
P[7:0]
Y0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
06234-
051
MPEG2
DECODER
CLKIN
P[7:0]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7390/
ADV7391
VSYNC,
HSYNC
8
2
YCrCb
06234-
052
3FF
00
XY
Cb0
Y0
Y1
Cr0
CLKIN
P[7:0]
06234-
053
相关PDF资料 |
PDF描述 |
|---|---|
| ADV7511KSTZ | IC XMITTER HDMI 12BIT 100LQFP |
| ADV7511WBSWZ | IC XMITTER HDMI AUTO 64LQFP |
| ADV7622BSTZ-RL | IC TXRX HDMI 4:1 144LQFP |
| ADV7623BSTZ | IC TXRX HDMI 4:1 144LQFP |
| ADW54010Z-0REEL | IC SWITCH DUAL SPDT 10MSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADV7391BCPZ-REEL | 功能描述:IC VIDEO ENCODER SD/HD 32-LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 编码器，解码器，转换器 系列:- 产品变化通告:Development Systems Discontinuation 26/Apr/2011 标准包装:1 系列:- 类型:编码器 应用:DVB-S.2 系统 电压 - 电源，模拟:- 电压 - 电源，数字:- 安装类型:- 封装/外壳:模块 供应商设备封装:模块 包装:散装 其它名称:Q4645799 |
| ADV7391EBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391WBCPZ | 制造商:Analog Devices 功能描述: |
| ADV7391WBCPZ-RL | 制造商:Analog Devices 功能描述: |
| ADV7392 | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
发布紧急采购，3分钟左右您将得到回复。