参数资料
| 型号： | ADV7391BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 68/108页 |
| 文件大小： | 0K |
| 描述： | IC ENCODER VIDEO W/DAC 32LFCSP |
| 产品变化通告： | ADV734x, ADV739x Feature Improvement |
| 标准包装： | 1 |
| 类型： | 视频编码器 |
| 应用： | 机顶盒，视频播放器，显示器 |
| 电压 - 电源，模拟： | 2.6 V ~ 3.46 V |
| 电压 - 电源，数字： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ（5x5） |
| 包装： | 托盘 |
| 配用： | EVAL-ADV7391EBZ-ND - BOARD EVAL FOR ADV7391 ENCODER |
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ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 62 of 108
Figure 75. Input Signal to ED/HD Adaptive Filter
Figure 76. Output Signal from ED/HD Adaptive Filter (Mode A)
When the adaptive filter mode is changed to Mode B
(Subaddress 0x35, Bit 6), the output shown in Figure 77
can be obtained.
Figure 77. Output Signal from ED/HD Adaptive Filter (Mode B)
SD DIGITAL NOISE REDUCTION
Subaddress 0xA3 to Subaddress 0xA5
Digital noise reduction (DNR) is applied to the Y data only.
A filter block selects the high frequency, low amplitude compo-
nents of the incoming signal (DNR input select). The absolute
value of the filter output is compared to a programmable
threshold value (DNR threshold control). There are two DNR
modes available: DNR mode and DNR sharpness mode.
In DNR mode, if the absolute value of the filter output is
smaller than the threshold, it is assumed to be noise. A
programmable amount (coring gain border, coring gain data) of
this noise signal is subtracted from the original signal. In DNR
sharpness mode, if the absolute value of the filter output is less
than the programmed threshold, it is assumed to be noise as
before. However, if the level exceeds the threshold, now being
identified as a valid signal, a fraction of the signal (coring gain
border, coring gain data) is added to the original signal to boost
high frequency components and sharpen the video image.
In MPEG systems, it is common to process the video information
in blocks of 8 pixels × 8 pixels for MPEG2 systems or 16 pixels
× 16 pixels for MPEG1 systems (block size control). DNR can
be applied to the resulting block transition areas known to
contain noise. Generally, the block transition area contains two
pixels. It is possible to define this area to contain four pixels
(border area).
It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the DNR
block offset.
The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.
Figure 78. SD DNR Block Diagram
06234-
076
06234-
077
06234-
078
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
CORING GAIN DATA
CORING GAIN BORDER
GAIN
DNR CONTROL
FILTER
OUTPUT
> THRESHOLD?
INPUT FILTER
BLOCK
FILTER OUTPUT
< THRESHOLD
DNR OUT
+
MAIN SIGNAL PATH
ADD SIGNAL
ABOVE
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
DNR
SHARPNESS
MODE
NOISE
SIGNAL PATH
Y DATA
INPUT
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
CORING GAIN DATA
CORING GAIN BORDER
GAIN
DNR CONTROL
FILTER
OUTPUT
< THRESHOLD?
INPUT FILTER
BLOCK
FILTER OUTPUT
> THRESHOLD
DNR OUT
MAIN SIGNAL PATH
SUBTRACT
SIGNAL IN
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
DNR MODE
NOISE
SIGNAL PATH
Y DATA
INPUT
–
+
06234-
079
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADV7391BCPZ-REEL | 功能描述:IC VIDEO ENCODER SD/HD 32-LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 编码器，解码器，转换器 系列:- 产品变化通告:Development Systems Discontinuation 26/Apr/2011 标准包装:1 系列:- 类型:编码器 应用:DVB-S.2 系统 电压 - 电源，模拟:- 电压 - 电源，数字:- 安装类型:- 封装/外壳:模块 供应商设备封装:模块 包装:散装 其它名称:Q4645799 |
| ADV7391EBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391WBCPZ | 制造商:Analog Devices 功能描述: |
| ADV7391WBCPZ-RL | 制造商:Analog Devices 功能描述: |
| ADV7392 | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
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