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参数资料
型号： ADZS-BF561-MMSKIT
厂商： Analog Devices Inc
文件页数： 20/64页
文件大小： 0K
描述： KIT STARTER MULTIMEDIA BF561
产品培训模块： Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
Multimedia Starter Kit
标准包装： 1
系列： Blackfin®
类型： DSP：视频
适用于相关产品： ADSP-BF561
所含物品： 多媒体 SDK 光盘、子板和 ADSP-BF5xx EZ-LITE 评估板
相关产品： ADSP-BF561SKBCZ-6V-ND - IC DSP 32BIT 600MHZ 256CSPBGA
ADSP-BF561SKBCZ-5V-ND - IC DSP 32BIT 500MHZ 256CSPBGA
ADSP-BF561SKBCZ-5A-ND - IC DSP CTLR 32BIT BKFN 256CSPBGA
ADSP-BF561SKBCZ-6A-ND - IC DSP CTRLR 32B 600MHZ 256CPBGA
ADSP-BF561SBBCZ-5A-ND - IC DSP CTRLR 32B 500MHZ 256CPBGA
ADSP-BF561SBBZ500-ND - IC PROCESSOR 500MHZ 297-PBGA
ADSP-BF561SBBZ600-ND - IC DSP 32BIT 600MHZ 297-BGA
ADSP-BF561SKBZ600-ND - IC DSP 32BIT 600MHZ 297PBGA
ADSP-BF561SKBZ500-ND - IC DSP 32BIT 500MHZ 297PBGA
ADSP-BF561SKB600-ND - IC DSP CTRLR 32BIT 600MHZ 297BGA
更多...
其它名称： ADDS-BF561-MMSKIT
ADDS-BF561-MMSKIT-ND
ADSP-BF561 
SPECIFICATIONS
Component specifications are subject to change without notice.
OPERATING CONDITIONS
Parameter
Conditions
Min
Nominal
Max
Unit
V DDINT
V DDINT
V DDINT
V DDEXT
V DDEXT
V IH
V IL
T J
T J
Internal Supply Voltage 1
Internal Supply Voltage 3
Internal Supply Voltage 3
External Supply Voltage
External Supply Voltage
High Level Input Voltage 4, 5
Low Level Input Voltage 5
Junction Temperature
Junction Temperature
Non automotive 500 MHz and 533 MHz speed grade models 2
600 MHz speed grade models 2
Automotive grade models 2
Non automotive grade models 2
Automotive grade models 2
256-Ball CSP_BGA (12 mm × 12 mm) @ T AMBIENT = 0°C to +70°C
256-Ball CSP_BGA (17 mm × 17 mm) @ T AMBIENT = 0°C to +70°C
0.8
0.8
0.95
2.25
2.7
2.0
–0.3
0
0
1.25
1.35
1.25
2.5, or 3.3
3.3
1.375
1.4185
1.375
3.6
3.6
3.6
+0.6
+105
+95
V
V
V
V
V
V
V
°C
°C
T J
Junction Temperature
256-Ball CSP_BGA (17 mm × 17 mm) @ T AMBIENT =–40°C to +85°C –40
+115
°C
T J
T J
Junction Temperature
Junction Temperature
297-Ball PBGA @ T AMBIENT = 0°C to +70°C
297-Ball PBGA @ T AMBIENT = –40°C to +85°C
0
–40
+95
+115
°C
°C
1
2
3
4
5
Internal voltage (V DDINT ) regulator tolerance is –5% to +10% for all models. 
See Ordering Guide on Page 63 . 
The internal voltage regulation feature is not available. External voltage regulation is required to ensure correct operation. 
The ADSP-BF561 is 3.3 V tolerant (always accepts up to 3.6 V maximum V IH ), but voltage compliance (on outputs, V OH ) depends on the input V DDEXT , because V OH (maximum)  
approximately equals V DDEXT (maximum). This 3.3 V tolerance applies to bidirectional and input only pins.
Applies to all signal pins.
Table 9 and Table 10 describe the timing requirements for the
ADSP-BF561 clocks (t CCLK = 1/f CCLK ). Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
(VCO) operating frequencies, as described in Absolute Maxi-
mum Ratings on Page 22 . Table 11 describes phase-locked loop
operating conditions.
core clock, system clock, and Voltage Controlled Oscillator
Table 9. Core Clock (CCLK) Requirements—500 MHz and 533 MHz Speed Grade Models 1
Parameter
Max
Unit
f CCLK
f CCLK
f CCLK
f CCLK
f CCLK
f CCLK
CCLK Frequency (V DDINT = 1.235 Vminimum) 2
CCLK Frequency (V DDINT = 1.1875 Vminimum)
CCLK Frequency (V DDINT = 1.045 Vminimum)
CCLK Frequency (V DDINT = 0.95 Vminimum)
CCLK Frequency (V DDINT = 0.855 Vminimum) 3
CCLK Frequency (V DDINT = 0.8 V minimum) 3
533
500
444
350
300
250
MHz
MHz
MHz
MHz
MHz
MHz
1
2
3
See Ordering Guide on Page 63 . 
External Voltage regulation is required on automotive grade models (see Ordering Guide on Page 63 ) to ensure correct operation. 
Not applicable to automotive grade models. See Ordering Guide on Page 63 . 
Table 10. Core Clock (CCLK) Requirements—600 MHz Speed Grade Models 1
Parameter
Max
Unit
f CCLK
f CCLK
f CCLK
f CCLK
f CCLK
f CCLK
f CCLK
CCLK Frequency (V DDINT = 1.2825 V minimum) 2
CCLK Frequency (V DDINT = 1.235 V minimum)
CCLK Frequency (V DDINT = 1.1875 V minimum)
CCLK Frequency (V DDINT = 1.045 V minimum)
CCLK Frequency (V DDINT = 0.95 V minimum)
CCLK Frequency (V DDINT = 0.855 V minimum)
CCLK Frequency (V DDINT = 0.8 V minimum)
600
533
500
444
350
300
250
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1
2
See Ordering Guide on Page 63 . 
External voltage regulator required to ensure proper operation at 600 MHz. 
Rev. E |
Page 20 of 64 |
September 2009
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相关代理商/技术参数
参数描述
ADZS-BF561-MMSKIT 制造商:Analog Devices 功能描述:MEDIA KIT ((NW))
ADZS-BF592-EZLITE 功能描述:KIT EVAL EZ LITE ADZS-BF592 RoHS:是 类别:编程器，开发系统 >> 通用嵌入式开发板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 产品培训模块:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色产品:Blackfin? BF50x Series Processors 标准包装:1 系列:Blackfin® 类型:DSP 适用于相关产品:ADSP-BF548 所含物品:板，软件，4x4 键盘，光学拨轮，QVGA 触摸屏 LCD 和 40G 硬盘 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相关产品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
ADZS-BF592-EZLITE 制造商:Analog Devices 功能描述:ADZS-BF592-EZLITE
ADZS-BF608-EZLITE 制造商:Analog Devices 功能描述:DIGITAL SIGNAL PROCESSOR - DEVELOPMENT TOOL
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