参数资料
型号: AGLE3000V5-FGG484
厂商: Microsemi SoC
文件页数: 3/166页
文件大小: 0K
描述: IC FPGA IGLOOE 1.5V 484FPBGA
标准包装: 60
系列: IGLOOe
逻辑元件/单元数: 75264
RAM 位总计: 516096
输入/输出数: 341
门数: 3000000
电源电压: 1.425 V ~ 1.575 V
安装类型: 表面贴装
工作温度: 0°C ~ 70°C
封装/外壳: 484-BGA
供应商设备封装: 484-FPBGA(23x23)
其它名称: 1100-1118
IGLOOe DC and Switching Characteristics
2-86
Revision 13
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-38 Timing Model and Waveforms
PRE
CLR
Out
CLK
Data
EN
tSUE
50%
tSUD
tHD
50%
tCLKQ
0
tHE
tRECPRE
tREMPRE
tRECCLR
tREMCLR
tWCLR
tWPRE
tPRE2Q
tCLR2Q
tCKMPWH tCKMPWL
50%
Table 2-137 Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std.
Units
tCLKQ
Clock-to-Q of the Core Register
0.89
ns
tSUD
Data Setup Time for the Core Register
0.81
ns
tHD
Data Hold Time for the Core Register
0.00
ns
tSUE
Enable Setup Time for the Core Register
0.73
ns
tHE
Enable Hold Time for the Core Register
0.00
ns
tCLR2Q
Asynchronous Clear-to-Q of the Core Register
0.60
ns
tPRE2Q
Asynchronous Preset-to-Q of the Core Register
0.62
ns
tREMCLR
Asynchronous Clear Removal Time for the Core Register
0.00
ns
tRECCLR
Asynchronous Clear Recovery Time for the Core Register
0.24
ns
tREMPRE
Asynchronous Preset Removal Time for the Core Register
0.00
ns
tRECPRE
Asynchronous Preset Recovery Time for the Core Register
0.23
ns
tWCLR
Asynchronous Clear Minimum Pulse Width for the Core Register
0.30
ns
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
0.30
ns
tCKMPWH
Clock Minimum Pulse Width HIGH for the Core Register
0.56
ns
tCKMPWL
Clock Minimum Pulse Width LOW for the Core Register
0.56
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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