参数资料
| 型号： | AGLE600V5-FGG484I |
| 厂商： | Microsemi SoC |
| 文件页数： | 24/166页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1KB FLASH 600K 484-FBGA |
| 标准包装： | 60 |
| 系列： | IGLOOe |
| 逻辑元件/单元数： | 13824 |
| RAM 位总计： | 110592 |
| 输入/输出数： | 270 |
| 门数： | 600000 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 484-BGA |
| 供应商设备封装： | 484-FPBGA（23x23） |
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IGLOOe Device Family Overview
1-6
Revision 13
SRAM and FIFO
IGLOOe devices have embedded SRAM blocks along their north and south sides. Each variable-aspect-
ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2,
and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with
different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single
bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation
mode) using the UJTAG macro.
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
IGLOOe devices provide designers with very flexible clock conditioning capabilities. Each member of the
IGLOOe family contains six CCCs, each with an integrated PLL.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC
(center west side) has a PLL.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz
Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz
2 programmable delay types for clock skew minimization
Clock frequency synthesis
Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration.
Output duty cycle = 50% ± 1.5% or better
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used
Maximum acquisition time is 300 s
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
fOUT_CCC
Global Clocking
IGLOOe devices have extensive support for multiple clocking domains. In addition to the CCC and PLL
support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
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相关代理商/技术参数 |
参数描述 |
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| AGLE600V5-FGG896 | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
| AGLE600V5-FGG896ES | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:IGLOOe Low-Power Flash FPGAs with Flash Freeze Technology |
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