参数资料
型号: AGLE600V5-FGG484I
厂商: Microsemi SoC
文件页数: 70/166页
文件大小: 0K
描述: IC FPGA 1KB FLASH 600K 484-FBGA
标准包装: 60
系列: IGLOOe
逻辑元件/单元数: 13824
RAM 位总计: 110592
输入/输出数: 270
门数: 600000
电源电压: 1.425 V ~ 1.575 V
安装类型: 表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 484-BGA
供应商设备封装: 484-FPBGA(23x23)
IGLOOe Low Power Flash FPGAs
Revision 13
5-5
Revision 6 (Feb 2009)
Product Brief v1.3
The "Pro (Professional) I/O" section was revised to add two bullets regarding
wide range power supply voltage support.
3.0 V was added to the list of supported voltages in the "Pro I/Os with Advanced
Revision 5 (Oct 2008)
Product Brief v1.2
The Quiescent Current values in Table 1 IGLOOe Product Family table were
updated.
Revision 4 (Jul 2008)
Product Brief v1.1
DC
and
Switching
Characteristics
Advance v0.3
As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core
voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to
1.5 V.
N/A
Revision 3 (Jun 2008)
DC
and
Switching
Characteristics
Advance v0.2
Tables have been updated to reflect default values in the software. The default
I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V
I/O set.
DDR Tables have two additional data points added to reflect both edges for Input
DDR setup and hold time.
The power data table has been updated to match SmartPower data rather then
simulation values.
N/A
Table 2-144 IGLOOe CCC/PLL Specification was updated to add VMV to the
VCCI parameter row and remove the word "output" from the parameter
description for VCCI. Table note 3 was added.
parameter. Table note 9 is new.
Temperature1, the maximum operating junction temperature was changed from
110° to 100°.
title of the table was revised to remove "as measured on quiet I/Os." Table note 2
was revised to remove "estimated SSO density over cycles." Table note 3 was
deleted.
Levels is new.
EQ 2 was updated. The temperature was changed to 100°C, and therefore the
end result changed.
remove VMV and include PDC6 and PDC7. VCCI and VJTAG were removed
from the statement about IDD in the table note for Table 2-11 Quiescent Supply
Flash*Freeze Mode1 was updated to include VCCPLL. Note 4 was updated to
include PDC6 and PDC7.
pin) – Default I/O Software Settings and referenced for 1.2 V LVCMOS.
Revision
Changes
Page
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