参数资料
| 型号： | AGLE600V5-FGG484I |
| 厂商： | Microsemi SoC |
| 文件页数： | 66/166页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1KB FLASH 600K 484-FBGA |
| 标准包装： | 60 |
| 系列： | IGLOOe |
| 逻辑元件/单元数： | 13824 |
| RAM 位总计： | 110592 |
| 输入/输出数： | 270 |
| 门数： | 600000 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 484-BGA |
| 供应商设备封装： | 484-FPBGA（23x23） |
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Datasheet Information
5-2
Revision 13
Revision 10
(April 2012)
In Table 2-2 Recommended Operating Conditions 1, VPUMP programming voltage for
operation was changed from "0 to 3.45 V" to "0 to 3.6 V" (SAR 32256). Values for
VCCPLL at 1.2–1.5 V DC core supply voltage were changed from "1.14 to 1.26 V" to
"1.14 to 1.575 V" (SAR 34701).
The tables in the "Quiescent Supply Current" section were updated with revised notes
on IDD. Table 2-8 Power Supply State per Mode is new (SARs 34745, 36949).
(example) (SAR 37105).
"TBD" for 3.3 V LVCMOS Wide Range in Table 2-28 I/O Output Buffer Maximum
Resistances1 and Table 2-30 I/O Short Currents IOSH/IOSL was replaced by "Same
as regular 3.3 V LVCMOS" (SAR 33855). Values were also added for 1.2 V LVCMOS
and 1.2 V LVCMOS Wide Range.
The formulas in the table notes for Table 2-29 I/O Weak Pull-Up/Pull-Down
Resistances were corrected (SAR 34753).
IOSH and IOSL values were added to 3.3 V LVCMOS Wide Range Table 2-40
Minimum and Maximum DC Input and Output Levels, and 1.2 V LVCMOS Wide Range
Figure 2-48 FIFO Read and Figure 2-49 FIFO Write have been added (SAR 34844).
Characteristics" section and Output DDR "Timing Characteristics" section (SAR 34802).
Minimum pulse width High and Low values were added to the tables in the "Global Tree
Timing Characteristics" section. The maximum frequency for global clock parameter
was removed from these tables because a frequency on the global is only an indication
of what the global network can do. There are other limiters such as the SRAM, I/Os, and
PLL. SmartTime software should be used to determine the design frequency (SAR
36952).
Revision 9
(March 2012)
revised to clarify that although no existing security measures can give an absolute
guarantee, Microsemi FPGAs implement the best security available in the industry (SAR
34665).
The Y security option and Licensed DPA Logo were added to the "IGLOOe Ordering
Information" section. The trademarked Licensed DPA Logo identifies that a product is
covered by a DPA counter-measures license from Cryptography Research (SAR
34725).
The following sentence was removed from the "Advanced Architecture" section:
"In addition, extensive on-chip programming circuitry allows for rapid, single-voltage
(3.3 V) programming of IGLOOe devices via an IEEE 1532 JTAG interface" (SAR
34685).
The "Specifying I/O States During Programming" section is new (SAR 34696).
Values for VCCPLL at 1.5 V DC core supply voltage were changed from "1.4 to 1.6 V" to
"1.425 to 1.575 V" in Table 2-2 Recommended Operating Conditions 1 (SAR 32292).
The reference to guidelines for global spines and VersaTile rows, given in the "Global
Clock Contribution—PCLOCK" section, was corrected to t
he "Spine Architecture"
section of the Global Resources chapter in the IGLOOe FPGA Fabric User's Guide
(SAR 34731).
Revision
Changes
Page
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