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参数资料
型号： AGLE600V5-FGG484I
厂商： Microsemi SoC
文件页数： 71/166页
文件大小： 0K
描述： IC FPGA 1KB FLASH 600K 484-FBGA
标准包装： 60
系列： IGLOOe
逻辑元件/单元数： 13824
RAM 位总计： 110592
输入/输出数： 270
门数： 600000
电源电压： 1.425 V ~ 1.575 V
安装类型： 表面贴装
工作温度： -40°C ~ 85°C
封装/外壳： 484-BGA
供应商设备封装： 484-FPBGA（23x23）
Datasheet Information
5-6
Revision 13
Revision 3 (cont’d)
Table 2-14 Summary of I/O Output Buffer Power (per pin) – Default I/O Software
Settings1 was updated to change PDC3 to PDC7. The table notes were updated
to reflect that power was measured on VCCI. Table note 4 is new.
2-10
Table 2-16 Different Components Contributing to the Static Power Consumption
in IGLOO Devices and Table 2-18 Different Components Contributing to the
Static Power Consumption in IGLOO Devices were updated to add PDC6 and
PDC7, and to change the definition for PDC5 to bank quiescent power.
2-11, 2-12
A table subtitle was added for Table 2-18 Different Components Contributing to
the Static Power Consumption in IGLOO Devices.
2-12
The "Total Static Power Consumption—PSTAT" section was updated to revise the
calculation of PSTAT, including PDC6 and PDC7.
2-13
Footnote 1 was updated to include information about PAC13. The PLL
Contribution equation was changed from: PPLL = PAC13 + PAC14 * FCLKOUT to
PPLL = PDC4 + PAC13 * FCLKOUT.
2-14
The "Timing Model" was updated to be consistent with the revised timing
numbers.
2-16
In Table 2-22 Summary of Maximum and Minimum DC Input Levels, TJ was
changed to TA in notes 1 and 2.
2-22
Table 2-22 Summary of Maximum and Minimum DC Input Levels was updated
to included a hysteresis value for 1.2 V LVCMOS (Schmitt trigger mode).
2-22
All AC Loading figures for single-ended I/O standards were changed from
Datapaths at 35 pF to 5 pF.
N/A
The "1.2 V LVCMOS (JESD8-12A)" section is new.
2-47
Revision 2 (Jun 2008)
Product Brief v1.0
The product brief section of the datasheet was divided into two sections and
given a version number, starting at v1.0. The first section of the document
includes features, benefits, ordering information, and temperature and speed
grade offerings. The second section is a device family overview.
N/A
Revision 2 (cont’d)
Packaging v1.1
The naming conventions changed for the following pins in the "FG484" for the
A3GLE600:
Pin Number
New Function Name
J19
IO45PPB2V1
K20
IO45NPB2V1
M2
IO114NPB6V1
N1
IO114PPB6V1
N4
GFC2/IO115PPB6V1
P3
IO115NPB6V1
4-6
Revision 1 (Mar 2008)
Product Brief rev. 1
The "Low Power" section was updated to change "1.2 V and 1.5 V Core Voltage"
to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 25 W)" was removed
from "Low Power Active FPGA Operation."
1.2_V was added to the list of core and I/O voltages in the "Pro (Professional) I/O"
and "Pro I/Os with Advanced I/O Standards" section sections.
I
I, 1-7
Revision 0 (Jan 2008) This document was previously in datasheet Advance v0.4. As a result of moving
to the handbook format, Actel has restarted the version numbers. The new
version number is 51700096-001-0.
N/A
Revision
Changes
Page
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