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参数资料
| 型号： | AM29DS163DT120WAK |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | 16 Megabit CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory |
| 中文描述： | 16兆位的CMOS 1.8伏只，同时作业快闪记忆体 |
| 文件页数： | 11/50页 |
| 文件大小： | 1682K |
| 代理商： | AM29DS163DT120WAK |
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Am29DS163D
11
A D V A N C E I N F O R M A T I O N
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
See
“Requirements for Reading Array Data” on
page 10
for more information. Refer to the
Table on
page 36
for timing specifications and to
Figure 13, on
page 36
for the timing diagram. I
CC1
in the DC Charac-
teristics table represents the active current
specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to
“Word/Byte Configuration” on page 10
for more information.
The device features an
Unlock Bypass
mode to facili-
tate faster programming. Once a bank enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word or byte, instead of four. The
“Word/Byte Configuration” section contains details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device.
Table 3 on page 13
to
Table 6 on page 14
indicate the address space that
each sector occupies. The device address space is di-
vided into two banks: Bank 1 contains the
boot/parameter sectors, and Bank 2 contains the
larger, code sectors of uniform size. A “bank address”
is the address bits required to uniquely select a bank.
Similarly, a “sector address” is the address bits re-
quired to uniquely select a sector.
I
CC2
in the DC Characteristics table represents the ac-
tive current specification for the write mode. The
“AC
Characteristics” on page 36
section contains timing
specification tables and timing diagrams for write
operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily intended to allow faster manufacturing throughput
at the factory.
If the system asserts V
HH
on this pin, the device auto-
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
V
HH
from the WP#/ACC pin returns the device to nor-
mal operation. Note that the WP#/ACC pin must not be
at V
HH
for operations other than accelerated program-
ming, or device damage may result. In addition, the
WP#/ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to
“Autoselect Mode” on page 15
and
“Autoselect Command Sequence” on page 23
for
more information.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased).
Figure 20, on page 42
shows how read and
write cycles may be initiated for simultaneous opera-
tion with zero latency. I
CC6
and I
CC7
in the DC
Characteristics table represent the current specifica-
tions for read-while-program and read-while-erase,
respectively.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
CC
± 0.3 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# are held at V
IH
, but not within
V
CC
± 0.3 V, the device is in the standby mode, but the
standby current is greater. The device requires stan-
dard access time (t
CE
) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics table represents the
standby current specification.
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