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参数资料
| 型号： | AM29F800BB-70SD |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | Flash Memory IC; Memory Size:8Mbit; Package/Case:44-SOIC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes |
| 中文描述： | 512K X 16 FLASH 5V PROM, 70 ns, PDSO44 |
| 封装： | LEAD FREE, MO-180AA, SOP-44 |
| 文件页数： | 10/45页 |
| 文件大小： | 1402K |
| 代理商： | AM29F800BB-70SD |
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Am29F800B
21504E6 March 3, 2009
D A TA SH EE T
Any commands written to the chip during the Embed-
ded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately ter-
minates the operation. The Chip Erase command se-
quence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
The system can determine the status of the erase
operation by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses are no longer latched.
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two un-
lock cycles, followed by a set-up command. Two addi-
tional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. The Command Definitions table
shows the address and data requirements for the sec-
tor erase command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 s begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time be-
tween these additional cycles must be less than 50 s,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 s, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase
Timer” section.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the op-
eration. The Sector Erase command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
tus of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to “Write Operation Status” for informa-
tion on these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristics” section for parameters, and to
the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 s time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase Sus-
pend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 s to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
See “Write Operation Status” for information on these
status bits.
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
相关PDF资料 |
PDF描述 |
|---|---|
| AM29F800BB-90ED | FLASH BOTTOM BLOCK 8MB, SMD, 29F800; Memory type:Bottom Block; Memory size:8Mbit; Memory configuration:1Mx8 or 512Kx16; Time, access:90ns; Voltage, Memory Vcc:5V; Case style:TSOP; Temperature, operating range:0(degree C) to RoHS Compliant: Yes |
| AM29F800BB-90EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
| AM29F800BB-90SC | Flash Memory IC; Access Time, Tacc:90ns; Package/Case:44-SO; Leaded Process Compatible:No; Memory Configuration:512K x 16 / 1M x 8; Memory Size:8Mbit; Peak Reflow Compatible (260 C):No; Supply Voltage Max:5.5V RoHS Compliant: No |
| AM29F800BB-90SD | Flash Memory IC; Memory Size:8Mbit; Package/Case:44-SOIC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
| AM29F800BB-90SF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:44-SOIC; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29F800BB-70SD | 制造商:Spansion 功能描述:FLASH MEMORY IC |
| AM29F800BB-70SE | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 8Mbit 1M/512K x 8bit/16bit 70ns 44-Pin SO |
| AM29F800BB-70SF | 功能描述:闪存 8M (1MX8/512KX16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AM29F800BB-70SI | 制造商:Spansion 功能描述:8M CMOS FLASH 5V |
| AM29F800BB-90EC | 制造商:Spansion 功能描述:8M CMOS FLASH 5V |
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