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参数资料
| 型号： | AM29F800BB-70SD |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | Flash Memory IC; Memory Size:8Mbit; Package/Case:44-SOIC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:70ns; Series:AM29 RoHS Compliant: Yes |
| 中文描述： | 512K X 16 FLASH 5V PROM, 70 ns, PDSO44 |
| 封装： | LEAD FREE, MO-180AA, SOP-44 |
| 文件页数： | 8/45页 |
| 文件大小： | 1402K |
| 代理商： | AM29F800BB-70SD |
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14
Am29F800B
21504E6 March 3, 2009
D A TA SH EE T
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection measures prevent accidental erasure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during VCC power-up and
power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not ac-
cept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or se-
quences into the command register initiates device op-
erations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the im-
proper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or Em-
bedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The sys-
tem can read array data using the standard read tim-
ings, except that if it reads at an address within erase-
suspended sectors, the device outputs status data.
After completing a programming operation in the Erase
Suspend mode, the system may once again read array
data with the same exception. See “Erase Sus-
pend/Erase Resume Commands” for more information
on this mode.
The system must issue the reset command to re-en-
able the device for reading array data if DQ5 goes high,
or while in the autoselect mode. See the “Reset Com-
mand” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the de-
vice to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the se-
quence cycles in an erase command sequence before
erasing begins. This resets the device to reading array
data. Once erasure begins, however, the device ig-
nores reset commands until the operation is complete.
The reset command may be written between the se-
quence cycles in a program command sequence be-
fore programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the se-
quence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to read-
ing array data (also applies during Erase Suspend).
相关PDF资料 |
PDF描述 |
|---|---|
| AM29F800BB-90ED | FLASH BOTTOM BLOCK 8MB, SMD, 29F800; Memory type:Bottom Block; Memory size:8Mbit; Memory configuration:1Mx8 or 512Kx16; Time, access:90ns; Voltage, Memory Vcc:5V; Case style:TSOP; Temperature, operating range:0(degree C) to RoHS Compliant: Yes |
| AM29F800BB-90EF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:48-TSOP; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
| AM29F800BB-90SC | Flash Memory IC; Access Time, Tacc:90ns; Package/Case:44-SO; Leaded Process Compatible:No; Memory Configuration:512K x 16 / 1M x 8; Memory Size:8Mbit; Peak Reflow Compatible (260 C):No; Supply Voltage Max:5.5V RoHS Compliant: No |
| AM29F800BB-90SD | Flash Memory IC; Memory Size:8Mbit; Package/Case:44-SOIC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
| AM29F800BB-90SF | Flash Memory IC; Leaded Process Compatible:Yes; Memory Size:8Mbit; Package/Case:44-SOIC; Peak Reflow Compatible (260 C):Yes; Supply Voltage Max:5V; Access Time, Tacc:90ns; Series:AM29 RoHS Compliant: Yes |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM29F800BB-70SD | 制造商:Spansion 功能描述:FLASH MEMORY IC |
| AM29F800BB-70SE | 制造商:Spansion 功能描述:NOR Flash Parallel 5V 8Mbit 1M/512K x 8bit/16bit 70ns 44-Pin SO |
| AM29F800BB-70SF | 功能描述:闪存 8M (1MX8/512KX16) Parallel NOR Fl 5V RoHS:否 制造商:ON Semiconductor 数据总线宽度:1 bit 存储类型:Flash 存储容量:2 MB 结构:256 K x 8 定时类型: 接口类型:SPI 访问时间: 电源电压-最大:3.6 V 电源电压-最小:2.3 V 最大工作电流:15 mA 工作温度:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体: 封装:Reel |
| AM29F800BB-70SI | 制造商:Spansion 功能描述:8M CMOS FLASH 5V |
| AM29F800BB-90EC | 制造商:Spansion 功能描述:8M CMOS FLASH 5V |
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