- 您现在的位置：买卖IC网 > PDF目录295065 > AM79C965KCW (ADVANCED MICRO DEVICES INC) 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 PDF资料下载
参数资料
| 型号： | AM79C965KCW |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 138/220页 |
| 文件大小： | 1197K |
| 代理商： | AM79C965KCW |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页当前第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页第211页第212页第213页第214页第215页第216页第217页第218页第219页第220页
AMD
P R E L I M I N A R Y
24
Am79C965
SHFBUSY
Shift Busy
Output
The function of the SHFBUSY signal is to indicate when
the last byte of the EEPROM contents has been shifted
out of the EEPROM on the EEDO signal line. This infor-
mation is useful for
external EEPROM-programmable
registers that do not use the microwire protocol, as is
described herein: When the PCnet-32 controller is
performing a serial read of the EEPROM through the
microwire interface, the SHFBUSY signal will be driven
HIGH. SHFBUSY can serve as a serial shift enable to
allow the EEPROM data to be serially shifted into an
external device or series of devices. The SHFBUSY
signal will remain actively driven HIGH until the end of
the EEPROM read operation. If the EEPROM check-
sum was verified, then the SHFBUSY signal will be
driven LOW at the end of the EEPROM read operation.
If the EEPROM checksum verification failed, then the
SHFBUSY signal will remain HIGH. This function effec-
tively demarcates the end of a successful EEPROM
read operation and therefore is useful as a programma-
ble-logic
low-active output enable signal. For more de-
tails on external EEPROM-programmable registers,
see the
EEPROM Microwire Access section under
Hardware Access.
This pin can be controlled by the host system by writing
to BCR19, bit 3 (EBUSY).
SLEEP
Sleep
Input
When
SLEEP input is asserted (active LOW), the
PCnet-32 controller performs an internal system reset of
the S_RESET type and then proceeds into a power
savings mode. (The reset operation caused by
SLEEP
assertion will not affect BCR registers.) All outputs will
be placed in their normal S_RESET condition. During
sleep mode, all PCnet-32 controller inputs will be ig-
nored except for the
SLEEP pin itself. De-assertion of
SLEEP results in wake-up. The system must refrain
from starting the network operations of the PCnet-32
controller for 0.5 seconds following the deassertion of
the
SLEEP signal in order to allow internal analog cir-
cuits to stabilize.
Both LCLK and XTAL1 inputs must have valid clock
signals present in order for the
SLEEP command to take
effect.
If
SLEEP is asserted while LREQ is asserted, then the
PCnet-32 controller will perform an internal system
S_RESET and then wait for the assertion of
LGNT.
When
LGNT is asserted, the LREQ signal will be deas-
serted and then the PCnet-32 controller will proceed to
the power savings mode. Note that the internal system
S_RESET will not cause the
LREQ signal to be
deasserted.
The
SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that
SLEEP be asserted
at power up time, then the system must delay the
assertion of
SLEEP until three LCLK cycles after the
completion of a valid pin
RESET operation.
XTAL1–XTAL2
Crystal Oscillator Inputs
Input/Output
The crystal frequency determines the network data rate.
The PCnet-32 controller supports the use of quartz
crystals to generate a 20 MHz frequency compatible
with the ISO 8802-3 (IEEE/ANSI 802.3) network fre-
quency tolerance and jitter specifications. See the sec-
tion
External Crystal Characteristics (in section
Manchester Encoder/Decoder) for more detail.
The network data rate is one-half of the crystal fre-
quency. XTAL1 may alternatively be driven using an
external CMOS level source, in which case XTAL2 must
be left unconnected. Note that when teh PCnet-32 con-
troller is in coma mode, there is an internal 22 K
resis-
tor from XTAL1 to ground. If an external source drives
XTAL1, some power will be consumed driving this resis-
tor. If XTAL1 is driven LOW at this time power consump-
tion will be minimized. In this case, XTAL1 must remain
active for at least 30 cycles after the assertion of
SLEEP
and deassertion of
LREQ.
Microwire EEPROM Interface
EESK
EEPROM Serial Clock
Output
The EESK signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the microwire interface protocol. EESK is con-
nected to the microwire EEPROM’s Clock pin. It is con-
trolled by either the PCnet-32 controller directly during a
read of the entire EEPROM, or indirectly by the host
system by writing to BCR19, bit 1.
EESK can be used during programming of
external
EEPROM-programmable registers that do not use the
microwire protocol as follows:
When the PCnet-32 controller is performing a serial
read of the IEEE Address EEPROM through the
microwire interface, the SHFBUSY signal will serve as a
serial shift enable to allow the EEPROM data to be
serially shifted into an external device or series of de-
vices. This same signal can be used to gate the
output of
the programmed logic to avoid the problem of releasing
intermediate values to the rest of the system board logic.
The EESK signal can serve as the clock, and EEDO will
serve as the input data stream to the programmable
shift register.
EEDO
EEPROM Data Out
Input
The EEDO signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the microwire interface protocol. EEDO is con-
nected to the microwire EEPROM’s Data Output pin. It
相关PDF资料 |
PDF描述 |
|---|---|
| AM80A-024L-120F18 | 1-OUTPUT 240 W DC-DC REG PWR SUPPLY MODULE |
| AJ80A-024L-033F50 | 1-OUTPUT 240 W DC-DC REG PWR SUPPLY MODULE |
| AM93LC66S | 4096-bits Serial Electrically Erasable PROM |
| AM93LC66SA | 4096-bits Serial Electrically Erasable PROM |
| AM93LC66VN | 4096-bits Serial Electrically Erasable PROM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM79C970 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
发布紧急采购，3分钟左右您将得到回复。