AMD
P R E L I M I N A R Y
114
Am79C965
EEPROM-Programmable Registers
The following registers contain configuration informa-
tion that will be programmed automatically during the
EEPROM read operation:
1) I/O offsets 0h–Fh
Address PROM locations
2) BCR2
Miscellaneous
Configuration register
3) BCR16
I/O Base Address Lower
4) BCR17
I/O Base Address Upper
5) BCR18
Burst Size and Bus
Control Register
6) BCR21
Interrupt Control Register
If the PREAD bit (BCR19) is reset to ZERO
and the
PVALID bit (BCR19) is reset to ZERO, then the
EEPROM read has experienced a failure and the con-
tents of the EEPROM programmable register will be set
to default H_RESET values. At this point, the PCnet-32
controller will enter Software Relocatable Mode.
Note that accesses to the Address PROM I/O locations
do not directly access the Address EEPROM itself. In-
stead, these accesses are routed to a set of “shadow”
registers on board the PCnet-32 controller that are
loaded with a copy of the EEPROM contents during the
automatic read operation that immediately follows the
H_RESET operation.
EEPROM MAP
The automatic EEPROM read operation will access 18
words (i.e. 36 bytes) of the EEPROM. The format of the
EEPROM contents is shown in Table 39, beginning with
the byte that resides at the lowest EEPROM address.
Table 39. EEPROM Content
EEPROM
Word
Byte
MSB
Byte
LSB
Addr
(Most Significant Byte)
Addr
(Lease Significant Byte)
0
1
2nd byte of the ISO 8802-3
0
First byte of the ISO 8802-3
(Lowest
(IEEE/ANSI 802.3) station physical
Address)
address for this node
address for this node, where first byte
refers to the first byte to appear on the
802.3 medium
1
3
4th byte of the node address
2
3rd byte of the node address
2
5
6th byte of the node address
4
5th byte of the node address
3
7
Reserved location:
must be 00h
6
Reserved location:
must be 00h
4
9
Hardware ID: must be 10h if
8
Driver IRQ: Must be programmed to the
compatibility to AMD drivers is desired
system IRQ channel number being used
if AMD drivers are used.
5
B
User programmable space
A
User programmable space
6
D
MSB of two-byte checksum, which is the
C
LSB of two-byte checksum, which is
sum of bytes 0-B and bytes E and F
the sum of bytes 0-B and bytes E and F
7
F
Must be ASCII “W” (57h) if compatibility
E
Must be ASCII “W” (57h) if compatibility
to AMD driver software is desired
8
11
BCR16[15:8] (I/O Base Address Lower)
10
BCR16[7:0] (I/O Base Address Lower)
9
13
BCR17[15:8] (I/O Base Address Upper)
12
BCR17[7:0] (I/O Base Address Upper)
A
15
BCR18[15:8] (Burst Size and Bus Control)
14
BCR18[7:0] (Burst Size and
Bus Control)
B
17
BCR2[15:8] (Miscellaneous configuration)
16
BCR2[7:0] (Miscellaneous configuration)
C
19
BCR21[15:8] (Interrupt Control)
18
BCR21[7:0] (Interrupt Control)
D
1B
Reserved location:
must be 00h
1A
Reserved location:
must be 00h
E
1D
Reserved location:
must be 00h
1C
Reserved location:
must be 00h
F
1F
checksum
adjust byte for the first
1E
Reserved location:
must be 00h
36 bytes of the EEPROM contents;
checksum of the first 36 bytes of the
EEPROM should total to FFh
10
21
Reserved location:
must be 00h
20
Reserved location:
must be 00h
11
23
User programmable byte locations
22
User programmable byte locations
EEPROM Contents