- 您现在的位置：买卖IC网 > PDF目录295065 > AM79C965KCW (ADVANCED MICRO DEVICES INC) 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 PDF资料下载
参数资料
| 型号： | AM79C965KCW |
| 厂商： | ADVANCED MICRO DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封装： | PLASTIC, QFP-160 |
| 文件页数： | 195/220页 |
| 文件大小： | 1197K |
| 代理商： | AM79C965KCW |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页当前第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页第211页第212页第213页第214页第215页第216页第217页第218页第219页第220页
AMD
P R E L I M I N A R Y
76
Am79C965
Effect of AHOLD
Assertion of AHOLD during Linear Burst transfers will
cause the PCnet-32 controller to float some portion of
the address bus beginning at the next clock cycle. If
BRDY is returned while AHOLD is active, then the linear
burst sequence will continue until the current burst
would otherwise normally terminate, since the data bus
and the lower portion of the address bus may remain
active during AHOLD. However, a new linear burst se-
quence, requiring a new
ADS assertion, will not be
started while AHOLD is active.
When AHOLD is asserted during T1 of a linear burst,
then the linear burst operation will be suspended until
AHOLD is deasserted. Once AHOLD is deasserted,
then the PCnet-32 controller will start the suspended
linear burst with the intended address. See Figure 23.
(Note that the intended T1 of the linear burst sequence
has been labeled Ta in the figure, since a T1 was never
executed due to the suspension of the address bus re-
quired by the assertion of AHOLD.)
When AHOLD is asserted in the middle of a linear burst,
the linear burst may proceed without stalling or halting.
AHOLD requires that PCnet-32 controller float a portion
of its address bus, but linear burst data cycles will still
proceed, since the AHOLD signal only affects a portion
of the address bus, and that portion of the address bus is
not being used for the middle accesses of a linear burst.
However, if AHOLD is asserted in the middle of a linear
burst operation, and the AHOLD signal is held long
enough that a new linear burst sequence will start (a
new
ADS is to be issued by the PCnet-32 controller)
then at the end of the current linear sequence, the
PCnet-32 controller must wait for the AHOLD signal to
become inactive before beginning the next linear se-
quence, since the AHOLD signal would now interfere
with the PCnet-32 controller’s wish to assert
ADS and a
new address on the entire address bus. During the time
that the PCnet-32 controller is waiting for the release of
the AHOLD signal, the PCnet-32 controller will continue
to drive the command signals, but
ADS will be driven
inactive.
Note that if
RDYRTN is asserted during a linear burst se-
quence while AHOLD is active, then no more access will
be performed until AHOLD is deasserted. This is be-
cause the assertion of
RDYRTN will cause the
PCnet-32 controller to insert a new T1 cycle into the lin-
ear burst. A T1 cycle requires assertion of
ADS, but ADS
assertion is not allowed as long as AHOLD is still as-
serted. Therefore, the T1 cycle is delayed until the
AHOLD is deasserted.
The portion of the Address Bus that will be floated at the
time of an address hold operation will be determined by
the value of the Cache Line Length register (BCR18,
bits 15–11). Table 23 lists all of the legal values of CLL
showing the portion of the Address Bus that will become
floated during an address hold operation.
Table 23. CLL Value of Floated Address in AHOLD
Floated Portion of Address
Bus During AHOLD
00000
None
00001
A31–A2
00010
A31–A3
00011
Reserved CLL Value
00100
A31–A4
00101–00111
Reserved CLL Values
01000
A31–A5
01001–01111
Reserved CLL Values
10000
A31–A6
10001–11111
Reserved CLL Values
CLL Value
Note that the default value of CLL after H_RESET is
00100. All timing diagrams in this document are drawn
with the assumption that this is the value of CLL.
相关PDF资料 |
PDF描述 |
|---|---|
| AM80A-024L-120F18 | 1-OUTPUT 240 W DC-DC REG PWR SUPPLY MODULE |
| AJ80A-024L-033F50 | 1-OUTPUT 240 W DC-DC REG PWR SUPPLY MODULE |
| AM93LC66S | 4096-bits Serial Electrically Erasable PROM |
| AM93LC66SA | 4096-bits Serial Electrically Erasable PROM |
| AM93LC66VN | 4096-bits Serial Electrically Erasable PROM |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AM79C970 | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全称:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
发布紧急采购，3分钟左右您将得到回复。