Chapter 9
Cache Organization
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23542A/0—September 2000
AMD-K6-2E+ Embedded Processor Data Sheet
Preliminary Information
9.5
L2 Cache Testing
The AMD-K6-2E+ processor provides the L2AAR MSR that
allows for direct access to the L2 cache and L2 tag arrays. For
9.6
Cache-Line Fills
The processor performs a cache-line fill for any area of system
memory defined as cacheable. If an area of system memory is
not explicitly defined as uncacheable by the software or system
logic, or implicitly treated as uncacheable by the processor,
then the memory access is assumed to be cacheable.
Software can prevent caching of certain pages by setting the
PCD bit in the PDE or PTE. Additionally, software can define
regions of memory as uncacheable or write combinable by
programming the MTRRs in the UWCCR MSR (see
“Memorymemory is defined as uncacheable.
The system logic also has control of the cacheability of bus
cycles. If it determines the address is not cacheable, system
logic negates the KEN# signal when asserting the first BRDY#
or NA# of a cycle.
The processor does not cache certain memory accesses such as
locked operations. In addition, the processor does not cache
PDE or PTE memory reads in the L1 cache (referred to as page
table walks). However, page table walks are cached in the L2
cache if the PDE or PTE is determined to be cacheable.
When the processor needs to read memory, the processor drives
a read cycle onto the bus. If the cycle is cacheable, the
processor asserts CACHE#. If the cycle is not cacheable, a
non-burst, single-transfer read takes place. The processor waits
for the system logic to return the data and assert a single
the processor executes a 32-byte burst read cycle. The processor
expects a total of four BRDY# signals for a burst read cycle to