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Software Environment
Chapter 3
AMD-K6-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Preliminary Information
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mmreg1—MMX/3DNow! register defined by bits 5, 4, and 3
of the modR/M byte
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mmreg2—MMX/3DNow! register defined by bits 2, 1, and 0
of the modR/M byte
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mreg16/32—word or doubleword integer register, or word or
doubleword integer value in memory defined by the
modR/M byte
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mreg8—byte integer register or byte integer value in
memory defined by the modR/M byte
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reg8—byte integer register defined by instruction byte(s) or
bits 5, 4, and 3 of the modR/M byte
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reg16/32—word or doubleword integer register defined by
instruction byte(s) or bits 5, 4, and 3 of the modR/M byte
Opcode Bytes
The second and third columns list all applicable opcode bytes.
ModR/M Byte
The fourth column lists the modR/M byte when used by the
instruction. The modR/M byte defines the instruction as a
regi s t er or memory fo rm. If modR/M bi ts 7 an d 6 are
documented as mm (memory form), mm can only be 10b, 01b or
00b.
Decode Type
The fifth column lists the type of instruction decode — short,
long, and vector. The AMD-K6-2E+ processor decode logic can
process two short, one long, or one vector decode per clock.
RISC86 Operation
The sixth column lists the type of RISC86 operation(s) required
for the instruction. The operation types and corresponding
execution units are as follows:
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alu—either of the integer execution units
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alux—integer X execution unit only
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branch—branch condition unit
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float—floating-point execution unit
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limm—load immediate, instruction control unit
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load, fload, mload—load unit
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meu—multimedia execution units for MMX and 3DNow!
instructions
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store, fstore, mstore—store unit