Chapter 13
Test and Debug
253
23542A/0—September 2000
AMD-K6-2E+ Embedded Processor Data Sheet
Preliminary Information
s
TDO is never floated because the Boundary-Scan Test
Access Port must remain enabled at all times, including
during the Three-State Test mode.
The Three-State Test mode is exited when the processor
samples RESET asserted.
13.3
Boundary-Scan Test Access Port (TAP)
The boundary-scan Test Access Port (TAP) is an IEEE standard
that defines synchronous scanning test methods for complex
logic circuits, such as boards containing a processor. The
AMD-K6-2E+ processor supports the TAP standard defined in
th e I EEE Standard Te st Acces s Po rt and Bo undary-Scan
Architecture (IEEE 1149.1-1990) specification.
Boundary scan testing uses a shift register consisting of the
serial interconnection of boundary-scan cells that correspond to
each I/O buffer of the processor. This non-inverting register
chain, called a Boundary Scan Register (BSR), can be used to
capture the state of every processor pin and to drive every
processor output and bidirectional pin to a known state.
Each BSR of every component on a board that implements the
boundary-scan architecture can be serially interconnected to
enable component interconnect testing.
Test Access Port
The TAP consists of the following:
s
Test Access Port (TAP) Controller—The TAP controller is a
synchronous, finite state machine that uses the TMS and
TDI input signals to control a sequence of test operations.
TAP states and their definition.
s
Instruction Register (IR)—The IR contains the instructions
that select the test operation to be performed and the Test
s
Test Data Registers (TDR)—The three TDRs are used to
process the test data. Each TDR is selected by an instruction
page 255 for a list of these registers and their functions.