232
Write Merge Buffer
Chapter 10
AMD-K6-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Preliminary Information
UC/WC Cacheability
Control Register
(UWCCR)
The MTRRs are accessed by addressing the 64-bit MSR known
as the UC/WC Cacheability Control Register (UWCCR). The
MSR address of the UWCCR is C000_0085h. Following reset, all
bits in the UWCCR register are set to 0. MTRR0 (lower 32 bits
of the UWCCR register) defines the size and memory type of
range 0 and MTRR1 (upper 32 bits) defines the size and
.
Figure 87. UC/WC Cacheability Control Register (UWCCR)
Physical Base Address n (n=0, 1). T h i s address i s t h e 15 most-
significant bits of the physical base address of the memory
range. The least-significant 17 bits of the base address are not
needed because the base address is by definition always aligned
on a 128-Kbyte boundary.
Physical Address Mask n (n=0, 1). T h i s v a l u e is the 15 most-
significant bits of a physical address mask that is used to define
the size of the memory range. This mask is logically ANDed
with both the physical base address field of the UWCCR
register and the physical address generated by the processor. If
the results of the two AND operations are equal, then the
generated physical address is considered within the range.
That is, if:
Mask & Physical Base Address = Mask & Physical Address Generated
then, the physical address generated by the processor is in the
range.
16
0
63
Physical Address Mask 0
17
31
Physical Base Address 0
1
2
Physical Address Mask 1
Physical Base Address 1
32
33
34
48
49
U
C
0
W
C
0
U
C
1
W
C
1
MTRR1
MTRR0
Symbol
Description
Bits
UC0
Uncacheable Memory Type
0
WC0
Write-Combining Memory Type
1
Symbol
Description
Bits
UC1
Uncacheable Memory Type
32
WC1
Write-Combining Memory Type
33