Chapter 2
Internal Architecture
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23542A/0—September 2000
AMD-K6-2E+ Embedded Processor Data Sheet
Preliminary Information
2.6
Branch-Prediction Logic
Sophisticated branch logic that can minimize or hide the impact
of changes in program flow is designed into the AMD-K6-2E+
processor. Branches in x86 code fit into two categories:
s
Unconditional branches always change program flow (that is,
the branches are always taken)
s
Conditional branches may or may not divert program flow
(that is, the branches are taken or not-taken). When a
conditional branch is not taken, the processor simply
continues decoding and executing the next instructions in
memory.
Typical applications have up to 10% of unconditional branches
a n d anot he r 10 % to 20% condi ti onal branch es . T h e
AMD-K6-2E+ processor branch logic has been designed to
handle this type of program behavior and to minimize its
negative effects on instruction execution, such as stalls due to
delayed instruction fetching and the draining of the processor
pipeline. The branch logic contains an 8192-entry branch
history table, a 16-entry by 16-byte branch target cache, a
16-entry return address stack, and a branch execution unit.
Branch History Table
The AMD-K6-2E+ processor handles unconditional branches
without any penalty by redirecting instruction fetching to the
target address of the unc o nditional branch . Howeve r,
conditional branch es re quire the us e of the dy namic
branch-prediction mechanism built into the AMD-K6-2E+
processor.
A two-level adaptive history algorithm is implemented in an
8192-entry branch history table. This table stores executed
branch information, predicts individual branches, and predicts
the behavior of groups of branches.
To accomm o d ate the l a r g e branch his t ory ta ble , the
AMD-K6-2E+ processor does not store predicted target
addresses. Instead, the branch target addresses are calculated
on-the-fly using ALUs during the decode stage. The adders
calculate all possible target addresses before the instructions
are fully decoded and the processor chooses which addresses
are valid.