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AMD PowerNow! Technology
Chapter 6
AMD-K6-2E+ Embedded Processor Data Sheet
23542A/0—September 2000
Preliminary Information
Processor State
Observability
Register (PSOR)
To support AMD PowerNow! technology, all low-power versions
of the AMD-K6-2E+ processor provide a different version of the
Processor State Observability Register (PSOR), as shown in
Figure 57 and fully described in this section. All standard-
power versions of the processor support the PSOR register as
defined on
page 49. The PSOR register is MSR C000_0087h.
.
Figure 57. Processor State Observability Register (PSOR)—Low-Power Versions of the Processor
PBF[2:0] Field. This read-only field contains the BF divisor values
externally applied to the processor BF[2:0] pins. These input BF
values are sampled by the processor during the falling
transition of RESET.
Note: This BF divisor value may be different than the BF divisor
value supplied to the processor’s internal PLL.
VID Field. This read-only field contains the Voltage ID bits driven
to the processor VID[4:0] pins at RESET. These bits are
initialized to 01010b and driven on the VID[4:0] pins at RESET.
Note: Low-power
AMD-K6-2E+
processors
support
AMD
PowerNow! technology, which enables dynamic alteration of
the
processor’s
core
voltage.
See
for
information on programming the VID[4:0] pins.
NOL2 Bit. This read-only bit indicates whether the processor
contains an L2 cache. This bit is always set to 0 for the
AMD-K6-2E+ processor.
2
0
63
EBF[2:0]
Reserved
Symbol
Description
Bits
NOL2
No L2 Functionality
8
STEP
Processor Stepping
7-4
EBF
Effective Bus Frequency Divisor
2-0
3
4
STEP
7
8
9
N
O
L
2
VID
PBF[2:0]
16
20
23
21
15
24
Symbol
Description
Bits
PBF
Pin Bus Frequency Divisor
23-21
VID
Voltage ID
20-16