参数资料
型号: AMIS30623C6238G
厂商: ON Semiconductor
文件页数: 47/61页
文件大小: 0K
描述: IC MOTOR DRIVER/CTLR 20-SOIC
标准包装: 38
应用: 步进电机驱动器
评估套件: 可供
输出数: 1
电流 - 输出: 800mA
电源电压: 6.5 V ~ 29 V
工作温度: -40°C ~ 165°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
供应商设备封装: 20-SOIC
包装: 管件
AMIS ? 30623
GetFullStatus
This command is provided to the circuit by the LIN master
to get a complete status of the circuit and the stepper ? motor.
Refer to RAM Registers and Flags Table to see the meaning
of the parameters sent to the LIN master.
Note: A GetFullStatus command will attempt to reset flags
<TW> , <TSD> , <UV2> , <ElDef> , <StepLoss> ,
The master sends either type#7 or type#8 preparing frame.
GetFullStatus corresponds to 2 successive LIN
in ? frame responses with 0x3D indirect ID.
Note: It is not mandatory for the LIN master to initiate the
second in ? frame response if the data in the second response
frame is not needed by the application.
<CPFail> , <OVC1> , <OVC2> , <VddReset> , <Stall> ,
<AbsStall> , <DelStallLo> and <DelStallHi> .
1. The master sends a type #7 preparing frame. After the type#7 preparing frame, the master sends a reading frame
type#6 to retrieve the circuit’s in ? frame response.
Table 43. GetFullStatus PREPARING FRAME TYPE #7
Structure
Byte
0
Content
Identifier
Bit 7
*
Bit 6
*
Bit 5
0
Bit 4
ID4
Bit 3
ID3
Bit 2
ID2
Bit 1
ID1
Bit 0
ID0
1
2
3
Data 1
Data 2
Checksum
1
1
CMD[6:0] = 0x01
AD[6:0]
Checksum over data
Table 44. GetFullStatus READING FRAME TYPE #6 (1)
Structure
Byte
0
Content
Identifier
Bit 7
0
Bit 6
1
Bit 5
1
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
0
Bit 0
1
1
2
3
Data 1
Data 2
Data 3
1
Irun[3:0]
Vmax[3:0]
AD[6:0]
Ihold[3:0]
Vmin[3:0]
4
Data 4
AccShape
StepMode[1:0]
Shaft
Acc[3:0]
5
6
Data 5
Data 6
VddReset
StepLoss
Motion[2:0]
ElDef
UV2
ESW
TSD
OVC1
TW
OVC2
Tinfo[1:0]
Stall
CPFail
7
Data 7
1
1
1
1
TimeE
DataE
HeadE
BitE
8
9
Data 8
Checksum
AbsThr[3:0]
Checksum over data
DelThr[3:0]
Table 45. GetFullStatus READING FRAME TYPE #6 (2)
Structure
Byte
0
Content
Identifier
Bit 7
0
Bit 6
1
Bit 5
1
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
0
Bit 0
1
1
2
3
4
5
6
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
1
AD[6:0]
ActPos[15:8]
ActPos[7:0]
TagPos[15:8]
TagPos[7:0]
SecPos[7:0]
7
Data 7
FS2StallEn[2:0]
1
DC100
SecPos[10:8]
8
Data 8
AbsStall
DelStallLo
DelStallHi
MinSamples[2:0]
DC100StEn
PWMJEn
9
Checksum
Checksum over data
Where :
(*) According to parity computation
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