参数资料
型号: AS7C25512FT32A-85BIN
厂商: ALLIANCE SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: 512K X 32 STANDARD SRAM, 8.5 ns, PBGA165
封装: LEAD FREE, BGA-165
文件页数: 22/24页
文件大小: 574K
代理商: AS7C25512FT32A-85BIN
4/12/04, v. 1.0
Alliance Semiconductor
7 of 24
AS7C25512FT32A
AS7C25512FT36A
Synchronous truth table
CE01
1 X = don’t care, L = low, H = high
CE1
CE2
ADSP ADSC ADV WRITE[2]
2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all
BWx, BWE, GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information.
OE
Address accessed
CLK
Operation
DQ
HXXX
L
X
NA
L to H
Deselect
Hi
Z
L
X
L
X
NA
L to H
Deselect
Hi
Z
L
X
H
L
X
NA
L to H
Deselect
Hi
Z
L
X
H
L
X
NA
L to H
Deselect
Hi
Z
L
X
H
L
X
NA
L to H
Deselect
Hi
Z
L
H
L
X
L
External
L to H
Begin read
Q
L
H
L
X
H
External
L to H
Begin read
Hi
Z
L
H
L
H
L
X
H
L
External
L to H
Begin read
Q
L
H
L
H
L
X
H
External
L to H
Begin read
Hi
Z
XXXHH
L
H
L
Next
L to H
Continue read
Q
XXXHH
L
H
Next
L to H
Continue read
Hi
Z
XXXHH
H
L
Current
L to H
Suspend read
Q
XXXHH
H
Current
L to H
Suspend read
Hi
Z
HXXXH
L
H
L
Next
L to H
Continue read
Q
HXXXH
L
H
Next
L to H
Continue read
Hi
Z
HXXXH
H
L
Current
L to H
Suspend read
Q
HXXXH
H
Current
L to H
Suspend read
Hi
Z
L
H
L
H
L
X
L
X
External
L to H
Begin write
D3
3
For write operation following a READ,
OE must be HIGH before the input data set up time and held HIGH throughout the input hold time
XXXHH
L
X
Next
L to H
Continue write
D
HXXXH
L
X
Next
L to H
Continue write
D
XXXHH
H
L
X
Current
L to H
Suspend write
D
HXXXH
H
L
X
Current
L to H
Suspend write
D
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