参数资料
型号: AS7C25512FT32A-85BIN
厂商: ALLIANCE SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: 512K X 32 STANDARD SRAM, 8.5 ns, PBGA165
封装: LEAD FREE, BGA-165
文件页数: 7/24页
文件大小: 574K
代理商: AS7C25512FT32A-85BIN
4/12/04, v. 1.0
Alliance Semiconductor
15 of 24
AS7C25512FT32A
AS7C25512FT36A
TAP AC test conditions
TAP AC output load equivalent
TAP DC electrical characteristics and operating conditions
(+10oC < TJ < +110oC and +2.4V < VDD < +2.6V unless otherwise noted)
1. All voltage referenced to VSS(GND).
2. Overshoot: VIH(AC) VDD + 1.5V for t tKHKH/2
Undershoot:VIL(AC) ≥ -0.5 for t tKHKH/2
Power-up: VIH +2.6V and VDD 2.4V and VDDQ 1.4V for t 200ms
During normal operation, VDDQ must not exceed VDD. Control input signals (such as LD, R/W, etc.) may not have pulsed widths less than
tKHKL(Min) or operate at frequencies exceeding fKF(Max).
Description
Conditions
Symbol
Min
Max
Units
Notes
Input high (logic 1) voltage
VIH
1.7
VDD + 0.3
V
1, 2
Input low (logic 0) voltage
VIL
-0.3
0.7
V
1, 2
Input leakage current
0V
≤ VIN ≤ VDD
ILI
-5.0
5.0
A
Output leakage current
Outputs disabled,
0V
≤ VIN
VDDQ(DQx)
ILO
-5.0
5.0
A
Output low voltage
IOLC = 100AVOL1
0.2
V
1
Output low voltage
IOLT = 2mA
VOL2
0.7
V
1
Output high voltage
IOHS = -100AVOH1
2.1
V
1
Output high voltage
IOHT = -2mA
VOH2
1.7
V
1
Input pulse levels. . . . . . . . . . . . . . . Vss to 2.5V
Input rise and fall times. . . . . . . . . . . . . . . 1 ns
Input timing reference levels. . . . . . . . . . 1.25V
Output reference levels . . . . . . . . . . . . . . 1.25V
Test load termination supply voltage. . . . 1.25V
TDO
50
ZO=50
1.25V
20pF
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