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参数资料
| 型号： | AS7C25512FT32A-85BIN |
| 厂商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分类： | SRAM |
| 英文描述： | 512K X 32 STANDARD SRAM, 8.5 ns, PBGA165 |
| 封装： | LEAD FREE, BGA-165 |
| 文件页数： | 4/24页 |
| 文件大小： | 574K |
| 代理商： | AS7C25512FT32A-85BIN |
AS7C25512FT32A
AS7C25512FT36A
4/12/04, v. 1.0
Alliance Semiconductor
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Test data-in (TDI)
The TDI pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between
TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register,
see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
Test data-out (TDO)
The TDO output pin/ball serially clocks data-out from the registers. The output is active depending upon the current state of the TAP state
machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See the TAP
Controller State Diagram.)
Performing a TAP RESET
You can perform a RESET by forcing TMS high (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM
and can be performed while the SRAM is operating.
TAP registers
Registers are connected between the TDI and TDO pins/balls. They allow data to be scanned into and out of the SRAM test circuitry. Only
one register can be selected at a time through the instruction register. Data is serially loaded into the TDI pin/ball on the rising edge of TCK.
Data is output on the TDO pin/ball on the falling edge of TCK.
Instruction register
You can serially load three-bit instructions into the instruction register. The register is loaded when it is placed between the TDI and TDO
pins/balls as shown in the TAP Controller Block Diagram. The instruction register is loaded with the IDCODE instruction at power up and
also if the controller is placed in a reset state, as described in the previous section.
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault
isolation of the board-level series test data path.
Bypass register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-
bit register that can be placed between the TDI and TDO pins/balls. This allows data to be shifted through the SRAM with minimal delay.
The bypass register is set low (Vss) when the BYPASS instruction is executed.
Boundary scan register
The boundary scan register is connected to all the input and bidirectional pins/balls on the SRAM. The x36 configuration has a 72-bit-long
register and the x18 configuration has a 53-bit-long register.
The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then
placed between the TDI and TDO pins/balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/RELOAD, and
SAMPLE Z instructions can be used to capture the contents of the I/O ring.
The boundary scan order table shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM
package. The most significant bit (MSB) of the register is connected to TDI, and the least significant bit (LSB) is connected to TDO.
Identification (ID) register
The ID register has a vendor code and other information described in the Identification Register Definitions table. The ID register is loaded
with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The
IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AS7C25512FT32A-85TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 flowthrough burst synchronous SRAM |
| AS7C25512FT32A-85TQCN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 flowthrough burst synchronous SRAM |
| AS7C25512FT32A-85TQI | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 flowthrough burst synchronous SRAM |
| AS7C25512FT32A-85TQIN | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 flowthrough burst synchronous SRAM |
| AS7C25512FT36A-10TQC | 制造商:ALSC 制造商全称:Alliance Semiconductor Corporation 功能描述:2.5V 512K x 32/36 flowthrough burst synchronous SRAM |
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