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参数资料
| 型号： | AT83C5112 |
| 厂商： | Atmel Corp. |
| 英文描述： | 8-bit Microcontroller with A/D Converter |
| 中文描述： | 8位微控制器与A / D转换器 |
| 文件页数： | 19/97页 |
| 文件大小： | 1229K |
| 代理商： | AT83C5112 |
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19
AT8xC5112
4191B
–
8051
–
04/03
Table 13.
WDTPRG Register
WDTPRG Address (0A7h)
Reset value = XXX0 0000
Write only register
WDT During Power Down and
Idle
Power Down
In Power Down mode the oscillator stops, which means the WDT also stops. While in
Power Down mode the user does not need to service the WDT. There are 2 methods of
exiting Power Down mode: by a hardware reset or via a level activated external interrupt
which is enabled prior to entering Power Down mode. When Power Down is exited with
hardware reset, servicing the WDT should occur as normal whenever the AT8xC5112 is
reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held
low long enough for the oscillator to stabilize. When the interrupt is brought high, the
interrupt is serviced. To prevent the WDT from resetting the device while the interrupt
pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested
that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it
is best to reset the WDT just before entering powerdown.
Idle Mode
In Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT8xC5112 while in Idle mode, the user should always set up a timer that will periodi-
cally exit Idle, service the WDT, and re-enter Idle mode.
7
6
5
4
3
2
1
0
T4
T3
T2
T1
T0
S2
S1
S0
Bit
Number
Bit
Mnemonic
Description
7
T4
Reserved
Do not try to set this bit.
6
T3
5
T2
4
T1
3
T0
WDT overflow select bit
0: Overflow after 14 bits
1: Overflow after 10 bits
2
S2
WDT Time-out select bit 2
1
S1
WDT Time-out select bit 1
0
S0
WDT Time-out select bit 0
S2
S1 S0
0
0
1
1
0
0
1
1
Selected Time-out with T0=0
(2
14
- 1) machine cycles, 16.3 ms at 12 MHz
(2
15
- 1) machine cycles, 32.7 ms at 12 MHz
(2
16
- 1) machine cycles, 65.5 ms at 12 MHz
(2
17
- 1) machine cycles, 131 ms at 12 MHz
(2
18
- 1) machine cycles, 262 ms at 12 MHz
(2
19
- 1) machine cycles, 542 ms at 12 MHz
(2
20
- 1) machine cycles, 1.05 s at 12 MHz
(2
21
- 1) machine cycles, 2.09 s at 12 MHz
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
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