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参数资料
| 型号： | AT83C5112 |
| 厂商： | Atmel Corp. |
| 英文描述： | 8-bit Microcontroller with A/D Converter |
| 中文描述： | 8位微控制器与A / D转换器 |
| 文件页数： | 39/97页 |
| 文件大小： | 1229K |
| 代理商： | AT83C5112 |
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39
AT8xC5112
4191B
–
8051
–
04/03
Figure 14.
Full-Duplex Master-slave Interconnection
Master Mode
The SPI operates in Master mode. Only one Master SPI device can initiate transmis-
sions. Software begins the transmission from a Master SPI module by writing to the
Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is imme-
diately transferred to the shift register. The byte begins shifting out on MOSI pin under
the control of the serial clock, SCK. Simultaneously, another byte shifts in from the
Slave on the Master
’
s MISO pin. The transmission ends when the Serial Peripheral
transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes
set, the received byte from the Slave is transferred to the receive data register in
SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA)
with the SPIF bit set, and then reading the SPDAT.
When the pin SS is pulled down during a transmission, the data is interrupted and when
the transmission is established again, the data present in the SPDAT is present.
Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity
using two bits in the SPCON: the Clock POLarity (CPOL
(1)
) and the Clock PHAse
(CPHA
(1)
). CPOL defines the default SCK line level in idle state. It has no significant
effect on the transmission format. CPHA defines the edges on which the input data are
sampled and the edges on which the output data are shifted (Figure 15 and Figure 16).
The clock phase and polarity should be identical for the Master SPI device and the com-
municating Slave device.
Figure 15.
Data Transmission Format (CPHA = 0)
8-bit Shift register
ClockSPI
Master MCU
8-bit Shift register
MISO
MISO
MOSI
MOSI
SCK
SCK
VSS
VDD
SS
SS
Slave MCU
1.
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN =
’
0
’
).
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
bit6
bit5
bit4
bit3
bit2
bit1
MSB
LSB
1
3
2
4
5
6
7
8
Capture point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (internal)
SCK cycle number
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