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参数资料
| 型号： | AT83SND1CXXX-ROTUL |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface |
| 中文描述： | 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | GREEN, TQFP-80 |
| 文件页数： | 90/212页 |
| 文件大小： | 1684K |
| 代理商： | AT83SND1CXXX-ROTUL |
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90
4109J–8051–10/06
AT8xC51SND1C
The firmware should never write more Bytes than supported by the endpoint FIFO.
14.5
Control Transactions
14.5.1
Setup Stage
The DIR bit in the UEPSTAX register should be at 0.
Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP
bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate
that an Out packet with a Setup PID has been received on the Control endpoint. When the
RXSETUP bit has been set, all the other bits of the UEPSTAX register are cleared and an inter-
rupt is triggered if enabled.
The firmware has to read the Setup request stored in the Control endpoint FIFO before clearing
the RXSETUP bit to free the endpoint FIFO for the next transaction.
14.5.2
Data Stage: Control Endpoint Direction
The data stage management is similar to Bulk management.
A Control endpoint is managed by the USB controller as a full-duplex endpoint: IN and OUT. All
other endpoint types are managed as half-duplex endpoint: IN or OUT. The firmware has to
specify the control endpoint direction for the data stage using the DIR bit in the UEPSTAX
register.
If the data stage consists of INs, the firmware has to set the DIR bit in the UEPSTAX register
before writing into the FIFO and sending the data by setting to 1 the TXRDY bit in the
UEPSTAX register. The IN transaction is complete when the TXCMPL has been set by the
hardware. The firmware should clear the TXCMPL bit before any other transaction.
If the data stage consists of OUTs, the firmware has to leave the DIR bit at 0. The RXOUTB0
bit is set by hardware when a new valid packet has been received on the endpoint. The
firmware must read the data stored into the FIFO and then clear the RXOUTB0 bit to reset
the FIFO and to allow the next transaction.
To send a STALL handshake, see
“STALL Handshake” on page 92
.
14.5.3
Status Stage
The DIR bit in the UEPSTAX register should be reset at 0 for IN and OUT status stage.
The status stage management is similar to Bulk management.
For a Control Write transaction or a No-Data Control transaction, the status stage consists of
a IN Zero Length Packet (see
“Bulk/Interrupt IN Transactions in Standard Mode” on page
88
). To send a STALL handshake, see
“STALL Handshake” on page 92
.
For a Control Read transaction, the status stage consists of a OUT Zero Length Packet (see
“Bulk/Interrupt OUT Transactions in Standard Mode” on page 86
).
14.6
Isochronous Transactions
14.6.1
Isochronous OUT Transactions in Standard Mode
An endpoint should be first enabled and configured before being able to receive Isochronous
packets.
When an OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller.
This triggers an interrupt if enabled. The firmware has to select the corre Bulk-outsponding end-
point, store the number of data Bytes by reading the UBYCTX register. If the received packet is
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