- 您现在的位置：买卖IC网 > PDF目录381497 > AT83SND1CXXX-ROTUL (ATMEL CORP) Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface PDF资料下载
参数资料
| 型号： | AT83SND1CXXX-ROTUL |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface |
| 中文描述： | 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | GREEN, TQFP-80 |
| 文件页数： | 93/212页 |
| 文件大小： | 1684K |
| 代理商： | AT83SND1CXXX-ROTUL |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页当前第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页第191页第192页第193页第194页第195页第196页第197页第198页第199页第200页第201页第202页第203页第204页第205页第206页第207页第208页第209页第210页第211页第212页
93
4109J–8051–10/06
AT8xC51SND1C
Important note: when a Clear Halt Feature occurs for an endpoint, the firmware should reset this
endpoint using the UEPRST resgister in order to reset the data toggle management.
14.7.3
Start of Frame Detection
The SOFINT bit in the USBINT register is set when the USB controller detects a Start Of Frame
PID. This triggers an interrupt if enabled. The firmware should clear the SOFINT bit to allow the
next Start of Frame detection.
14.7.4
Frame Number
When receiving a Start Of Frame, the frame number is automatically stored in the UFNUML and
UFNUMH registers. The CRCOK and CRCERR bits indicate if the CRC of the last Start Of
Frame is valid (CRCOK set at 1) or corrupted (CRCERR set at 1). The UFNUML and UFNUMH
registers are automatically updated when receiving a new Start of Frame.
14.7.5
Data Toggle Bit
The Data Toggle bit is set by hardware when a DATA0 packet is received and accepted by the
USB controller and cleared by hardware when a DATA1 packet is received and accepted by the
USB controller. This bit is reset when the firmware resets the endpoint FIFO using the UEPRST
register.
For Control endpoints, each SETUP transaction starts with a DATA0 and data toggling is then
used as for Bulk endpoints until the end of the Data stage (for a control write transfer). The Sta-
tus stage completes the data transfer with a DATA1 (for a control read transfer).
For Isochronous endpoints, the device firmware should ignore the data-toggle.
14.8
Suspend/Resume Management
14.8.1
Suspend
The Suspend state can be detected by the USB controller if all the clocks are enabled and if the
USB controller is enabled. The bit SPINT is set by hardware when an idle state is detected for
more than 3 ms. This triggers a USB interrupt if enabled.
In order to reduce current consumption, the firmware can put the USB PAD in idle mode, stop
the clocks and put the C51 in Idle or Power-down mode. The Resume detection is still active.
The USB PAD is put in idle mode when the firmware clear the SPINT bit. In order to avoid a new
suspend detection 3ms later, the firmware has to disable the USB clock input using the SUSP-
CLK bit in the USBCON Register. The USB PAD automatically exits of idle mode when a wake-
up event is detected.
The stop of the 48 MHz clock from the PLL should be done in the following order:
1.
Disable of the 48 MHz clock input of the USB controller by setting to 1 the SUSPCLK bit
in the USBCON register.
2.
Disable the PLL by clearing the PLLEN bit in the PLLCON register.
14.8.2
Resume
When the USB controller is in Suspend state, the Resume detection is active even if all the
clocks are disabled and if the C51 is in Idle or Power-down mode. The WUPCPU bit is set by
hardware when a non-idle state occurs on the USB bus. This triggers an interrupt if enabled.
This interrupt wakes up the CPU from its Idle or Power-down state and the interrupt function is
then executed. The firmware will first enable the 48 MHz generation and then reset to 0 the
SUSPCLK bit in the USBCON register if needed.
相关PDF资料 |
PDF描述 |
|---|---|
| AT83SND2CDVX | Single-Chip MP3 Decoder with Full Audio Interface |
| AT83SND2CMP3 | Single-Chip MP3 Decoder with Full Audio Interface |
| AT83SND2CMP3_0605 | Single-Chip MP3 Decoder with Full Audio Interface |
| AT84AD001B | Dual 8-bit 1 Gsps ADC |
| AT84AD001BCTD | Dual 8-bit 1 Gsps ADC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AT83SND2C | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface |
| AT83SND2C_05 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface |
| AT83SND2C_06 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface |
| AT83SND2C-7FRIL | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface |
| AT83SND2C-7FRUL | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface |
发布紧急采购，3分钟左右您将得到回复。