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参数资料
| 型号： | AT83SND1CXXX-ROTUL |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface |
| 中文描述： | 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | GREEN, TQFP-80 |
| 文件页数： | 92/212页 |
| 文件大小： | 1684K |
| 代理商： | AT83SND1CXXX-ROTUL |
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4109J–8051–10/06
AT8xC51SND1C
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB
controller.
When the IN packet has been sent, the TXCMPL bit in the UEPSTAX register is set by the USB
controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit
before filling the endpoint FIFO with new data.
The firmware should never write more Bytes than supported by the endpoint FIFO
14.6.4
Isochronous IN Transactions in Ping-pong Mode
An endpoint should be first enabled and configured before being able to send Isochronous
packets.
The firmware should fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in the
UEPSTAX register to allow the USB controller to send the data stored in FIFO at the next IN
request concerning the endpoint. The FIFO banks are automatically switched, and the firmware
can immediately write into the endpoint FIFO bank 1.
If the TXRDY bit is not set when the IN request occurs, nothing will be sent by the USB
controller.
When the IN packet concerning the bank 0 has been sent, the TXCMPL bit is set by the USB
controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit
before filling the endpoint FIFO bank 0 with new data. The FIFO banks are then automatically
switched.
When the IN packet concerning the bank 1 has been sent, the TXCMPL bit is set by the USB
controller. This triggers a USB interrupt if enabled. The firmware should clear the TXCMPL bit
before filling the endpoint FIFO bank 1 with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by the firm-
ware. Until the TXRDY bit has been set by the firmware for an endpoint bank, the USB controller
won’t send anything at each IN requests concerning this bank.
The firmware should never write more Bytes than supported by the endpoint FIFO.
14.7
Miscellaneous
14.7.1
USB Reset
The EORINT bit in the USBINT register is set by hardware when a End Of Reset has been
detected on the USB bus. This triggers a USB interrupt if enabled. The USB controller is still
enabled, but all the USB registers are reset by hardware. The firmware should clear the EORINT
bit to allow the next USB reset detection.
14.7.2
STALL Handshake
This function is only available for Control, Bulk, and Interrupt endpoints.
The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake
at the next request of the Host on the endpoint selected with the UEPNUM register. The
RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first resseted to 0. The
bit STLCRC is set at 1 by the USB controller when a STALL has been sent. This triggers an
interrupt if enabled.
The firmware should clear the STALLRQ and STLCRC bits after each STALL sent.
The STALLRQ bit is cleared automatically by hardware when a valid SETUP PID is received on
a CONTROL type endpoint.
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