参数资料
型号: AT89C51SND2C-7FTUL
厂商: Atmel
文件页数: 104/160页
文件大小: 0K
描述: IC 8051 MCU FLASH 64K MP3 100BGA
标准包装: 260
系列: 89C
核心处理器: 8051
芯体尺寸: 8-位
速度: 40MHz
连通性: I²C,IDE/ATAPI,MMC,SPI,UART/USART,USB
外围设备: 音频,I²S,MP3,PCM,POR,WDT
输入/输出数: 32
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
RAM 容量: 2.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 3.3 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-TFBGA
包装: 托盘
其它名称: AT89C51SND2C7FTUL
DS785UM1
7-43
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
The STOP value is the horizontal down counter value at
which the HSYNCn signal becomes inactive (stops). When
the Horizontal counter counts down to the STOP value,
the HSYNCn signal goes inactive. Please refer to video
signalling timing diagrams in Figure 7-9 and Figure 7-10.
STRT:Start - Read/Write
The STRT value is the horizontal down counter value at
which the HSYNCn signal becomes active (starts). When
the Horizontal counter counts down to the STRT value, the
HSYNCn signal goes active (starts). Please refer to video
signalling timing diagrams in Figure 7-9 and Figure 7-10.
HActiveStrtStop
Address: 0x8003_0018
Default: 0x0000_0000
Definition: Horizontal Active period Start/Stop register
Note: When horizontal clock gating is required, set the STRT and STOP fields in the
HActiveStrtStop register to the STRT and STOP values in HClkStrtStop + 5. This is a
programming requirement that is easily overlooked.
Bit Descriptions:
RSVD:
Reserved - Unknown during read
STOP:
Stop - Read/Write
The STOP value is the value of the Horizontal down
counter at which the HACTIVE signal becomes inactive
(stops). This indicates the end of the active video portion
for the Horizontal line. Please refer to video signalling
timing diagrams in Figure 7-9 and Figure 7-10. HACTIVE
is an internal block signal. The active video interval is
controlled by the logical OR of VACTIVE and HACTIVE.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
STOP
15
14
13
12
11
10
987654
3210
RSVD
STRT
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